N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM) stores multi-bit-per-cell. Its memory cells can have N states (N>2) and data are stored as N-ary codes. N-3DMPROM has a larger storage density than the prior-art binary 3D-MPROM. One advantage of N-3DROM over other N-ary memory (e.g. multi-level-cell flash) is that its array efficiency can be kept high. N-3DMPROM could be geometry-defined, junction-defined, or a combination thereof.
1. An N-ary three-dimensional mask-programmable read-only memory, comprising:
a semiconductor substrate including transistors;
a plurality of mask-programmable memory levels vertically stacked above and coupled to said substrate through a plurality of contact vias inside said memory, each of said memory levels comprising a plurality of mask-programmable memory cells, each of said memory cells comprising a diode-like device, wherein said memory cells have at least N possible states with N>2, and memory cells in different states have different ranges of read current at a read voltage;
wherein said substrate further comprises means for converting data from said memory levels into binary.
2. The N-ary three-dimensional mask-programmable read-only memory according to claim 1 , wherein at least a portion of said converting means is located directly under at least one of said memory levels.
3. The N-ary three-dimensional mask-programmable read-only memory according to claim 1 , wherein memory cells in a same state have substantially the same structure, and memory cells in at least three different states have different structures.
4. The N-ary three-dimensional mask-programmable read-only memory according to claim 1 , wherein memory cells in a same state have substantially the same junction, and memory cells in at least two different states have different junctions.
5. The N-ary three-dimensional mask-programmable read-only memory according to claim 1 , further comprising means for limiting the read current through memory cell under read.
6. The N-ary three-dimensional mask-programmable read-only memory according to claim 1 , wherein at least two read voltages are applied in sequence to selected memory cells during read.
7. The N-ary three-dimensional mask-programmable read-only memory according to claim 1 , wherein N is an integral power of 2.
8. The N-ary three-dimensional mask-programmable read-only memory according to claim 1 , wherein N is a non-integral power of 2.
9. An N-ary three-dimensional mask-programmable read-only memory, comprising:
a semiconductor substrate including transistors;
a plurality of mask-programmable memory levels vertically stacked above and coupled to said substrate through a plurality of contact vias inside said memory, each of said memory levels comprising a plurality of mask-programmable memory cells and dummy cells, each of said cells comprising a diode-like device, wherein said memory cells have at least N possible states with N>2, and memory cells in different states have different ranges of read current at a read voltage;
wherein said substrate further comprises means for comparing a first input from a selected memory cell and a second input from at least a selected dummy cell.
10. The N-ary three-dimensional mask-programmable read-only memory according to claim 9 , wherein said second input is coupled to first and second dummy cells, said first dummy cell having a first one of said N possible states and said second dummy cell having a second one of said N possible states.
11. The N-ary three-dimensional mask-programmable read-only memory according to claim 9 , wherein memory cells in a same state have substantially the same structure, and memory cells in at least three different states have different structures.
12. The N-ary three-dimensional mask-programmable read-only memory according to claim 9 , wherein memory cells in a same state have substantially the same junction, and memory cells in at least two different states have different junctions.
13. An N-ary three-dimensional mask-programmable read-only memory, comprising:
a semiconductor substrate including transistors;
a plurality of mask-programmable memory levels vertically stacked above and coupled to said substrate through a plurality of contact vias inside said memory, each of said memory levels comprising a plurality of mask-programmable memory cells, each of said memory cells comprising an upper address-selection line, a lower address-select line and a diode-like device;
wherein said memory cells have at least N possible states with N>2, and memory cells in different states have different ranges of read current at a read voltage; memory cells in a same state have substantially the same structure, and memory cells in at least three different states have different structures.
14. The N-ary three-dimensional mask-programmable read-only memory according to claim 13 , wherein memory cells in a same state have substantially the same geometry, and memory cells in at least three different states have different geometries.
15. The N-ary three-dimensional mask-programmable read-only memory according to claim 13 , wherein said memory cell further comprises a contact-area smaller than the overlapping area between said lower and upper address-selection lines, wherein said contact-area is the smallest current conduction area in said memory cell.
16. The N-ary three-dimensional mask-programmable read-only memory according to claim 15 , wherein an edge of said contact-area aligns with an edge of said upper address-selection line.
17. The N-ary three-dimensional mask-programmable read-only memory according to claim 15 , wherein the sizes of contact-areas from different states are unevenly distributed.
18. An N-ary three-dimensional mask-programmable read-only memory, comprising:
a semiconductor substrate including transistors;
a plurality of mask-programmable memory levels vertically stacked above and coupled to said substrate through a plurality of contact vias inside said memory, each of said memory levels comprising a plurality of mask-programmable memory cells, each of said memory cells comprising an upper address-selection line, a lower address-select line and a diode-like device;
wherein said memory cells have at least N possible states with N>2, and memory cells in different states have different ranges of read current at a read voltage; memory cells in a same state have substantially the same junction, and memory cells in at least two different states have different junctions.
19. The N-ary three-dimensional mask-programmable read-only memory according to claim 18 , wherein said diode-like device has a doping profile, and memory cells in at least two different states have different doping profiles.
20. The N-ary three-dimensional mask-programmable read-only memory according to claim 18 , wherein memory cells in at least two different states have different structures.