Silicon wafer and process for the heat treatment of a silicon wafer

1. A process for the heat treatment of a multiplicity of silicon wafers with a diameter of at least 300 mm

said process comprising resting wafers on supports selected with regard to the upper yield stress of the wafer, and at predetermined heating and cooling rate, as follows:

a) for wafers having an upper yield stress of at least 0.6 MPa, measured at a temperature of 1200° C., in a vertical furnace,

resting the silicon wafers during the heat treatment on substrate holders which are in the form of a continuous concentric ring with an internal diameter of at most 250 mm and an external diameter which is at least equal to the diameter of the silicon wafers, the surfaces of the substrate holders on which the silicon wafers rest having a flatness with deviations in the range from 0.05 mm to 0.5 mm from an ideal leveled plan,

heating the silicon wafers, at the start of the heat treatment, to a target temperature in the range from 1100° C. to 1300° C. at a predetermined heating rate,

holding the silicon wafers at the target temperature for a period of from 30 minutes to 3 hours under an inert or reducing atmosphere, and

cooling the silicon wafers at a predetermined cooling rate,

wherein the predetermined heating and cooling rates RR (in ° C./minute) in the temperature range above 900° C. are selected as a function of the current temperature T (in ° C.) such that the following condition is satisfied:

| RR|≦ 5.8×10 −4 +0.229 ×T− 3.5902137×10 −4 ×T 2 +1.4195996×10 −7 ×T 3 ;

b) for wafers having an upper yield stress of at least 0.4 Mpa, measured at a temperature of 1200° C., in a vertical furnace,

resting the silicon wafers during the heat treatment on substrate holders which are in the form of a continuous concentric ring with an internal diameter of at most 250 mm and an external diameter which is at least equal to the diameter of the silicon wafers, and with an additional bearing surface in the center of the ring, the surfaces of the substrate holders on which the silicon wafers rest having a flatness with deviations in the range from 0.05 mm to 0.5 mm from an ideal leveled plan,

the silicon wafers, at the start of the heat treatment, are heated up to a target temperature in the range from 1100° C. to 1300° C. at a predetermined heating rate,

holding the silicon wafers at the target temperature for a period of 30 minutes to 3 hours under an inert or reducing atmosphere,

cooling the silicon wafers are then cooled at a predetermined cooling rate, and

the predetermined heating and cooling rates RR (in ° C./minute) in the temperature range above 900° C. are selected as a function of the current temperature T (in ° C.) in such a way that the following condition is satisfied:

| RR|≦ 7.649×10 2 −1.6928 ×T+ 1.28112×10 −3 ×T 2 −3.2306467×10 −7 ×T 3 ;

c) for wafers having an upper yield stress of at least 0.3 MPa, measured at a temperature of 1200° C., in a vertical furnace,

resting the silicon wafers during the heat treatment on substrate holders which are in the form of a plate with an external diameter which is at least equal to the diameter of the silicon wafers, the surfaces of the substrate holders on which the silicon wafers rest having a flatness with deviations in the range from 0.05 mm to 0.5 mm from an ideal leveled plane,

heating the silicon wafers, at the start of the heat treatment to a target temperature in the range from 1100° C. to 1300° C. at a predetermined heating rate,

holding the silicon wafers at the target temperature for a period of 30 minutes to 3 hours under an inert or reducing atmosphere,

cooling the silicon wafers at a predetermined cooling rate,

wherein the heating and cooling rate RR (in ° C./minute) in the temperature range above 900° C. is selected as a function of the current temperature T (in ° C.) in such a way that the following condition is satisfied;

| RR|≦ 9.258×10 2 −2.2317 ×T+ 1.79552×10 −3 ×T 2 −4.8169846×10 −7 ×T 3 .

2. The process of claim 1 embodiment a), in which the silicon wafers have an upper yield stress in the range from 0.6 MPa to 1.1 MPa, measured at a temperature of 1200° C.

3. The process of claim 2 , in which the silicon wafers, prior to the start of the heat treatment, have a nitrogen concentration of from 3·10 13 atoms/cm 3 to 8·10 14 atoms/cm 3 , an interstitial oxygen concentration of from 5.2·10 17 atoms/cm 3 to 7.5·10 17 atoms/cm 3 and a resistivity of from 2 mΩcm to 12 Ωcm.

4. The process of claim 1 , embodiment b), in which the silicon wafers have an upper yield stress in the range from 0.4 MPa to 0.8 MPa, measured at a temperature of 1200° C.

5. The process of claim 4 , in which the silicon wafers, prior to the start of the heat treatment, have a nitrogen concentration of from 3·10 13 atoms/cm 3 to 8·10 14 atoms/cm 3 , an interstitial oxygen concentration of from 5.2·10 17 atoms/cm 3 to 7.5·10 17 atoms/cm 3 and a resistivity of from 8 Ωcm to 60 Ωcm.

6. The process of claim 1 , embodiment c), in which the silicon wafers have an upper yield stress in the range from 0.3 MPa to 0.6 MPa, measured at a temperature of 1200° C.

7. The process of claim 6 , in which the silicon wafers, prior to the start of the heat treatment, have a nitrogen concentration of from 1·10 13 atoms/cm 3 to 1·10 14 atoms/cm 3 , an interstitial oxygen concentration of from 5.2·10 17 atoms/cm 3 to 7.5·10 17 atoms/cm 3 and a resistivity of from 40 Ωcm to 90 Ωcm.

8. The process of claim 1 , wherein the silicon wafers, prior to the start of the heat treatment, have a nitrogen concentration of at most 6·10 14 atoms/cm 3 .

9. The process of claim 1 , wherein the substrate holders on which the silicon wafers rest are mounted parallel above one another, at a pitch of from 7.5 to 15 mm, calculated from bearing surface to bearing surface, during the heat treatment.

10. The process of claim 1 , wherein the substrate holders have a mean roughness R a of from 0.15 μm to 0.5 μm.

11. The method of claim 1 , wherein the substrate holders comprise silicon carbide.

12. A silicon wafer which does not have any epitaxially deposited layer or any layer produced by joining to the silicon wafer, said silicon wafer having a nitrogen concentration of from 1·10 13 atoms/cm 3 to 8·10 14 atoms/cm 3 , an oxygen concentration of from 5.2·10 17 atoms/cm 3 to 7.5·10 17 atoms/cm 3 , a BMD density in the center of the thickness of the silicon wafer of from 3·10 8 cm −3 to 2·10 10 cm 3 , a cumulative total length of all linear slippages of no more than 3 cm and a cumulative total area of areal slippage regions of no more than 7 cm 2 , the front surface of the silicon wafer having fewer than 45 nitrogen-induced defects of a size of more than 0.13 μm LSE in a DNN channel, a layer with a thickness of at least 5 μm, in which no more than 1·10 4 COPs/cm 3 with a size of at least 0.09 μm occur, and a BMD-free layer with a thickness of at least 5 μm.

13. The silicon wafer of claim 12 , which has a nitrogen concentration of from 1·10 13 atoms/cm 3 to 6·10 14 atoms/cm 3 .

14. The silicon wafer of claim 12 , which has a diameter of 300 mm or greater.

15. A silicon wafer which does not have any epitaxially deposited layer or any layer produced by joining to the silicon wafer, said silicon wafer having a nitrogen concentration of from 1·10 13 atoms/cm 3 to 8·10 14 atoms/cm 3 , an oxygen concentration of from 5.2·10 17 atoms/cm 3 to 7.5·10 17 atoms/cm 3 , a BMD density in the center of the thickness of the silicon wafer of from 3·10 8 cm −3 to 2·10 10 cm 3 , a cumulative total length of all linear slippages of no more than 3 cm and a cumulative total area of areal slippage regions of no more than 7 cm 2 , the front surface of the silicon wafer having fewer than 45 nitrogen-induced defects of a size of more than 0.13 μm LSE in a DNN channel, a layer with a thickness of at least 5 μm, in which no more than 1·10 4 COPs/cm 3 with a size of at least 0.09 μm occur, and a BMD-free layer with a thickness of at least 5 μm;

wherein said silicon wafer has been heat treated in accordance with claim 1 .