Optimized transistor for imager device
View Patent ↗An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e. one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, while other transistors can have normal symmetrical (i.e, two-sided) active area extension regions (e.g., lightly doped drains) with resulting high performance and short gate lengths. The asymmetrical active area extension region of the transistor associated with the photodiode can serve to reduce dark current at the photoconversion device. The punch-through problem normally cured by a lightly doped drain is fixed at the transistor associated with the photoconversion device by adding a V t adjustment implant and/or increasing its gate length.
1. A CCD imager device, comprising:
an array of CCD pixel cells; and
an output circuit for supplying pixel signals from said array of CCD pixel cells, said output circuit comprising a first transistor comprising a channel region between a higher voltage side and a lower voltage side and a single active area extension region with a halo implant at said higher voltage side of said channel.
2. The CCD imager device of claim 1 , wherein the output circuit comprises an output gate at the array of CCD pixel cells, wherein said first transistor is on the opposite side of said output gate as said array of CCD pixel cells.
3. The CCD imager device of claim 1 , wherein the output circuit comprises other transistors with respective gate lengths spanning respective channels, wherein said first transistor has a gate length which is greater than the gate lengths of each other transistor of the output circuit.
4. The CCD imager device of claim 1 , further comprising a threshold voltage adjustment implant below a gate of said first transistor.
5. The CCD imager device of claim 1 , wherein said first transistor is a reset transistor.
6. The CCD imager device of claim 1 , wherein said first transistor is a source follower transistor.
7. The CCD imager device of claim 1 , wherein said first transistor is a reset transistor and said output circuit further comprises a second transistor comprising a channel region between a higher voltage side and a lower voltage side and a single active area extension region with a halo implant at said higher voltage side of said channel.
8. The CCD imager device of claim 1 , wherein said array of CCD pixel cells comprises a plurality of polysilicon transfer gates, wherein each of said polysilicon transfer gates has respective active area extension regions, halo implant regions, and n-type surface implants in a substrate supporting said polysilicon transfer gates.
9. The CCD imager device of claim 1 , wherein said first transistor further comprises an n-type surface implant region proximate the single active area extension region.
10. A CCD imager device comprising an output circuit for supplying pixel output signals from a CCD pixel array, said output circuit comprising at least one transistor gate with a single active area extension region at a side of said at least one transistor gate.
11. The CCD imager device of claim 10 , wherein said at least one transistor gate is of a reset transistor.
12. The CCD imager device of claim 10 , wherein said at least one transistor gate is of a source follower transistor.
13. A imager device, comprising:
a CCD pixel cell array, said array comprising a plurality of polysilicon transfer gates, each of said polysilicon transfer gates having respective symmetrical active area extension regions, halo implant regions, and n-type surface implants in the substrate; and
an output circuit for outputting signals from the CCD pixel cell array, said output circuit comprising:
a reset transistor comprising a single active area extension region, a halo implant region, and an n-type surface implant region at a higher voltage side of a reset transistor gate; and
a source follower transistor comprising a single active area extension region, a halo implant region, and an n-type surface implant region at a higher voltage side of a source follower transistor gate.