Semiconductor memory device

1. A semiconductor memory device having a built-in error detection and correction system, wherein

the error detection and correction system is formed to have a cyclic code, with which multiple error bits are correctable, wherein

the cyclic code is configured in such a manner that an information polynomial of degree k-1 has k terms (k is a maximal number of t-bit error correctable bits capable of being utilized as information bits) including d (=2 m , m: integer, d<k) terms being actually used as information bits and k-d terms being fixed as terms of “0”, and wherein

the “0”-fixed terms are selected in such manner that the computation amount of syndrome calculation decreases.

2. The semiconductor memory device according to claim 1 , wherein

the error detection and correction system is formed to have a t(≧2)-bit error correction BCH code over Galois field GF(2 m ), and wherein

the BCH code is configured in such a manner that the d degrees of the information polynomial are derived from the least side in a total sums of coefficient “1” of remainder polynomials used for calculation of multiple syndrome polynomials.

3. The semiconductor memory device according to claim 1 , wherein

the error detection and correction system is formed to have a 2-bit error correction BCH code over Galois field GF(2 8 ), and wherein

the BCH code is configured in such a manner that 128 degrees of the information polynomial are derived from the least side in a total sums of coefficient “1” of remainder polynomials obtained from X m (m=16 to 254) derived by irreducible polynomial used for calculation of multiple syndrome polynomials.

4. The semiconductor memory device according to claim 3 , wherein the error detection and correction system includes an error location searching part, and wherein

the error location searching part comprises:

a first data bus, to which coefficient data of syndrome polynomials S 1 (x) and S 3 (x) are output;

255 arithmetic processing units, in which first arithmetic operation p n (x)S 1 (x) and second arithmetic operation (S 1 (x)) 2 +S 3 (x 3 )/S 1 (x) are simultaneously executed in parallel within 144 units selected based on the coefficient data on the first data bus, the first arithmetic operation being executed between an error bit-corresponding division remainder p n (x) and syndrome polynomial S 1 (x) on the first data bus, the second arithmetic operation being executed for syndrome polynomials only;

a second data bus for outputting a calculation result of the second arithmetic operation in the arithmetic processing units;

144 parity check units operative to perform an adding operation between the data on the second data bus and the calculation result of the first arithmetic operation of the processing units; and

a decoder configured to compare these processing results of the parity check units with p 2n (x) to obtain a matched error bit location “n”.

5. The semiconductor memory device according to claim 4 , wherein said error detection and correction system further includes an error correcting part, and wherein

the error correcting part comprises:

a three-bit parity check circuit configured to perform addition processing between the calculation result of the first arithmetic operation in the error position searching circuit, coefficients S 1 (x) 2 and S 3 (x)/S 1 (x) on the second data bus; and

an inverter circuit for inverting a read data bit in accordance with the processing result of the three-bit parity check circuit.

6. The semiconductor memory device according to claim 1 , wherein

the device is a non-volatile semiconductor memory with electrically rewritable and non-volatile memory cells arranged therein.

7. The semiconductor memory device according to claim 6 , wherein

the non-volatile semiconductor memory comprises a cell array with NAND strings arranged therein, the NAND string including a plurality of memory cells connected in series.

8. A semiconductor memory device having a built-in error detection and correction system, which detects and corrects 2-bit errors by use of a BCH code, wherein

the error detection and correction system comprises:

an encoding part configured to generate check bits to be written into the cell array of the device together with to-be-written data;

a syndrome operating part configured to execute syndrome operation for read out data from the cell array;

an error location searching part configured to search error locations based on the operation result of the syndrome operating part; and

an error correcting part configured to invert a read out data bit at an error location detected in the error location searching part, and output it, and wherein

the encoding part is for dividing 254-degree data polynomial f(x)x 16 configured with to-be-written data being coefficients thereof by code generation polynomial g(x) defined as a product of two 8-degree primitive polynomials m 1 (x) and m 3 (x), which are prime with each other on Galois field GF(2 8 ), to obtain 15-degree remainder polynomial r(x), thereby selecting 16 coefficients thereof as check bits, and

in the encoding part, M+16 (M “255-16=239) terms corresponding to 16 check bits and M data bits to be error-corrected are selected from the data polynomial in such a way that the calculation scale in the syndrome operating part is made as small as possible.

9. The semiconductor memory device according to claim 8 , wherein

in the encoding part, based on a coefficient table of 15-degree remainder polynomial r(x), the M+16 terms corresponding to the check bits and data bits are selected in order from the least side of total numbers of degrees with coefficient “1 ”.

10. The semiconductor memory device according to claim 9 , wherein the 16 check bits are generated via parity check for the coefficients of the degrees selected in the data polynomial f(x)x 16 .

11. The semiconductor memory device according to claim 8 , wherein

the error location searching part comprises:

a first data bus, to which coefficient data of syndrome polynomials S 1 (x)and S 3 (x) are output;

255 arithmetic processing units, in which first arithmetic operation p n (x)S 1 (x) and second arithmetic operation (S 1 (x)) 2 +S 3 (x 3 )/S 1 (x) are simultaneously executed in parallel within 144 units selected based on the coefficient data on the first data bus, the first arithmetic operation being executed between an error bit-corresponding division remainder p n (x) and syndrome polynomial S 1 (x) on the first data bus, the second arithmetic operation being executed for syndrome polynomials only;

a second data bus for outputting a calculation result of the second arithmetic operation in the arithmetic processing units;

144 parity check units operative to perform an adding operation between the data on the second data bus and the calculation result of the first arithmetic operation of the processing units; and

a decoder configured to compare these processing results of the parity check units with p 2n (x) to obtain a matched error bit location “n”.

12. The semiconductor memory device according to claim 8 , wherein

the error correcting part comprises:

a three-bit parity check circuit configured to perform addition processing between the calculation result of the first arithmetic operation in the error location searching part, coefficients S 1 (x) 2 and S 3 (x)/S 1 (x) on the second data bus; and

an inverter circuit for inverting a read data bit in accordance with the processing result of the three-bit parity check circuit.

13. The semiconductor memory device according to claim 8 , wherein

the device is a non-volatile semiconductor memory with electrically rewritable and non-volatile memory cells arranged therein.

14. The semiconductor memory device according to claim 13 , wherein

the non-volatile semiconductor memory comprises a cell array with NAND strings arranged therein, the NAND string including a plurality of memory cells connected in series.