ESD device layout for effectively reducing internal circuit area and avoiding ESD and breakdown damage and effectively protecting high voltage IC
An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability. Accordingly, by properly adjusting the breakdown voltage of ESD device within I/O circuit, i.e. adjusting the distance between the edge of n-well and the battlement layout pattern of heavily doped regions, it will help to reduce the chip area and improve the ESD reliability.
1. A layout pattern for protecting a circuit from electrostatic discharge, comprising:
a first heavily doped region of a first doping type in a first well of said first doping type; and
a second heavily doped region of a second doping type in a second well of said second doping type, wherein said second heavily doped region comprises a battlement layout pattern having protruding ridges and recessed concave regions along a side directly facing a boundary between said first and said second wells,
wherein only the second well of the second doping type occupies entirely each of the recessed concave regions and extends continuously from each of the recessed concave regions to the boundary between said first well and said second well.
2. The layout pattern as claimed in claim 1 , wherein said first doping type is p type and said second doping type is n type.
3. The layout pattern as claimed in claim 1 , wherein said first doping type is n type and said second doping type is p type.
4. The layout pattern as claimed in claim 1 , wherein said first heavily doped region comprises a second battlement layout pattern having second recessed concave regions directly facing said boundary between said first and said second wells.
5. The layout pattern as claimed in claim 4 , wherein at least one concave region of the battlement layout pattern in said second heavily doped region is opposite to at least one of the second recessed concave regions of the second battlement layout pattern in said first heavily doped region.
6. A method of forming a layout pattern for protecting a circuit from electrostatic discharge, said method comprising the steps of:
forming a first heavily doped region of a first doping type in a first well of said first doping type; and
forming a second heavily doped region of a second doping type in a second well of said second doping type, wherein said second heavily doped region comprises a battlement layout pattern having protruding ridges and recessed concave regions along a side directly facing a boundary between said first and said second wells,
wherein only the second well of the second doping type occupies entirely each of the recessed concave regions and extends continuously from each of the recessed concave regions to the boundary between said first well and said second well.
7. The method as claimed in claim 6 , wherein said first doping type is p type and said second doping type is n type.
8. The method as claimed in claim 6 , wherein said first doping type is n type and said second doping type is p type.
9. The method as claimed in claim 6 , wherein said first heavily doped region comprises a second battlement layout pattern having second recessed concave regions facing said boundary between said first and said second wells.
10. The method as claimed in claim 9 , wherein at least one concave region of the battlement layout pattern in said second heavily doped region is opposite to at least one of the second recessed concave regions of the second battlement layout pattern in said first heavily doped region.
11. A layout pattern for protecting a circuit from electrostatic discharge, comprising:
a first well of a first doping type;
a second well of a second doping type;
a first heavily doped region of said first doping type in said first well; and
a second heavily doped region of said second doping type in said second well;
wherein said second heavily doped region comprises one or more recessed concave region along a side directly facing said first heavily doped region,
wherein only the second well of the second doping type occupies entirely each of the recessed concave regions and extends continuously from each of the recessed concave regions to the boundary between said first well and said second well.