Method of forming metal-oxide-semiconductor transistor

1. A method of forming metal-oxide-semiconductor (MOS) transistors, comprising:

providing a semiconductor substrate and two gate structures disposed on the semiconductor substrate, the semiconductor substrate defining a first active region and a second active region therein, the two gate structures positioned in the first active region and the second active region respectively, each of the active regions comprising a source region and a drain region on two opposite sides of the gate structure in the semiconductor substrate respectively;

performing a salicide process;

forming a stress buffer layer on the semiconductor substrate, the gate structures, the source regions and the drain regions; and

forming a stressed cap layer on the stress buffer layer, and a tensile stress of the stressed cap layer being larger than a tensile stress of the stress buffer layer.

2. The method of forming MOS transistors according to claim 1 , after the step of forming the stressed cap layer, further comprising:

removing the stressed cap layer positioned in the second active region, and the stress buffer layer positioned in the second active region; and

performing an activating process on the stressed cap layer.

3. The method of forming MOS transistors according to claim 1 , wherein the MOS transistor formed in the first active region is an N-type metal-oxide-semiconductor (NMOS) transistor, and the MOS transistor formed in the second active region is a P-type metal-oxide-semiconductor (PMOS) transistor.

4. The method of forming MOS transistors according to claim 1 , wherein a thickness of the stress buffer layer is in a range from 10 to 300 angstroms.

5. The method of forming MOS transistors according to claim 1 , wherein the tensile stress of the stress buffer layer is smaller than 1.52 Giga-Pascals (GPa).

6. The method of forming MOS transistors according to claim 1 , wherein the stressed cap layer comprises a silicon nitride layer.

7. The method of forming MOS transistors according to claim 1 , wherein the stressed cap layer comprises a multiple-layer structure.

8. The method of forming MOS transistors according to claim 1 , wherein the tensile stress of the stressed cap layer decreases from top to bottom gradually.

9. The method of forming MOS transistors according to claim 1 , wherein a ratio of a thickness of the stress buffer layer to a thickness of the stressed cap layer is smaller than 0.5.

10. The method of forming MOS transistors according to claim 1 , wherein the stress buffer layer comprises a silicon oxide layer.

11. The method of forming MOS transistors according to claim 1 , wherein the stress buffer layer comprises a silicon nitride layer.

12. The method of forming MOS transistors according to claim 11 , further comprising a step of forming a silicon oxide layer on the semiconductor substrate before the step of forming the stress buffer layer, wherein the silicon oxide layer covers the gate structures, the source regions and the drain regions.

13. The method of forming MOS transistors according to claim 1 , wherein the stressed cap layer is a contact etch stop layer (CESL).

14. The method of forming MOS transistors according to claim 1 , wherein each of the gate structures comprises a gate and a spacer positioned on the sidewall of the gate.

15. The method of forming MOS transistors according to claim 1 , wherein each of the gate structures comprises a gate without a spacer.

16. The method of forming MOS transistors according to claim 1 , wherein the stress buffer layer and the stressed cap layer are formed in one apparatus.

17. The method of forming MOS transistors according to claim 1 , wherein the stress buffer layer and the stressed cap layer are formed in different apparatuses.

18. A method of forming a MOS transistor, comprising:

providing a semiconductor substrate and a gate structure disposed on the semiconductor substrate;

forming a stress buffer layer on the semiconductor substrate and the gate structure;

forming a stressed cap layer on the stress buffer layer, a tensile stress of the stressed cap layer being larger than a tensile stress of the stress buffer layer;

performing an activating process on the stressed cap layer;

removing the stressed cap layer and the stress buffer layer; and

performing a salicide process.

19. The method of forming a MOS transistor according to claim 18 , wherein a thickness of the stress buffer layer is in a range from 10 to 300 angstroms.

20. The method of forming a MOS transistor according to claim 18 , wherein the tensile stress of the stress buffer layer is smaller than 1.52 GPa.

21. The method of forming a MOS transistor according to claim 18 , wherein the stressed cap layer comprises a silicon nitride layer.

22. The method of forming a MOS transistor according to claim 18 , wherein a ratio of a thickness of the stress buffer layer to a thickness of the stressed cap layer is smaller than 0.5.

23. The method of forming a MOS transistor according to claim 18 , wherein the stress buffer layer comprises a silicon oxide layer.

24. The method of forming a MOS transistor according to claim 18 , wherein the stress buffer layer comprises a silicon nitride layer.

25. The method of forming a MOS transistor according to claim 24 , further comprising a step of forming a silicon oxide layer on the semiconductor substrate before the step of forming the stress buffer layer, wherein the silicon oxide layer covers the gate structure, the source region and the drain region.

26. The method of forming a MOS transistor according to claim 18 , wherein the stressed cap layer is a poly stressor.