Method for transmitting packets in a wireless communication system and an apparatus using the same
A wireless communication apparatus includes a first interface, a packet memory, a shift register set, and a second interface. The first interface receives a plurality of packets and stores the plurality of packets in the packet memory. The addresses of the plurality of packets stored in the packet memory are recorded in the shift register set. The second interface reads the packets in the packet memory according to the addresses of the packets recorded in the shift register set and then sends to a receiver. After an acknowledge signals from the receiver is received, the addresses of the successfully transmitted packets are cleared from the shift register set.
1. A wireless communication apparatus, comprising:
a packet memory;
a first interface coupled to the packet memory, for receiving a packet and storing the packet in the packet memory;
a shift register set coupled to the first interface, for recording an address of the packet stored in the packet memory, the shift register set comprising a plurality of shift registers connected in series, the plurality of shift registers comprising a first shift register coupled to the first interface and a last shift register, each shift register having a valid bit for configuring the state of the shift register so as to transmit the address of the packet to the next shift register according to the valid bit of the next shift register; and
a second interface coupled to the packet memory and the last shift register of the shift register set, for configuring the valid bits of the shift register set according to an acknowledge (ACK) signal of sending the packet, and accessing the shift register set so as to read and send the packet stored in the packet memory according to the address of the packet recorded in the shift register set.
2. The wireless communication apparatus of claim 1 , wherein the first interface records the address of the packet in the first shift register according to the valid bit of the first shift register.
3. The wireless communication apparatus of claim 1 , wherein the second interface checks the valid bits of the shift register set from the last shift register.
4. The wireless communication apparatus of claim 3 , wherein the second interface reads the address of the packet recorded in the shift register set according to a result of checking the valid bits of the shift register set.
5. The wireless communication apparatus of claim 1 , wherein the first interface comprises a direct memory access (DMA) interface.
6. The wireless communication apparatus of claim 1 , wherein the second interface comprises a medium access control (MAC) or a physical layer (PHY).
7. A method of transmitting packets in a wireless communication system, comprising:
receiving a plurality of packets;
storing the plurality of packets in a packet memory;
utilizing a shift register set to record addresses of the packets stored in the packet memory and inputting the address of the packet in a first shift register of the shift register set according to the order of receiving the plurality of packets;
moving the address of the packet to the next shift register when the next shift register has no address of the packet
reading and sending the plurality of packets stored in the packet memory according to the addresses of the plurality of packets; and
clearing the addresses of the packets according to an acknowledge (ACK) signal of sending the plurality of packets.
8. The method of claim 7 , wherein reading and sending the plurality of packets stored in the packet memory according to the addresses of the plurality of packets is reading and sending the plurality of packets stored in the packet memory according to the result of checking the successive shift registers having the addresses of the packets from the last shift register of the shift register set.
9. The method of claim 7 , wherein clearing the addresses of the packets according to the ACK signal of sending the plurality of packets is configuring the shift registers recording the addresses of the packets to no address according to the ACK signal of sending the plurality of packets.