Display device and semiconductor device
View Patent ↗An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
1. A semiconductor device comprising:
a gate wiring;
a wiring provided between adjacent pixel electrodes; and
a thin film transistor,
wherein the gate wiring is arranged so as to cross the wiring,
wherein a channel formation region of the thin film transistor is provided under the wiring,
wherein the channel formation region is provided at a position overlapping with the wiring at least partly, and
wherein a channel width of the channel formation region is longer than a channel length of the channel formation region.
2. The semiconductor device according to claim 1 , wherein a longitudinal direction of an impurity region connecting the channel formation regions is parallel to a channel width direction.
3. The semiconductor device according to claim 1 , wherein the channel formation region is at least one of an amorphous semiconductor and a polycrystalline semiconductor.
4. The semiconductor device according to claim 1 , wherein the thin film transistor includes a plurality of channel formation regions.
5. The semiconductor device according to claim 1 , wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the adjacent pixel electrodes, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the wiring.
6. The semiconductor device according to claim 1 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a longitudinal direction of a region of the wiring which overlapping with the channel formation region.
7. The semiconductor device according to claim 1 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a direction in which current flows through the wiring.
8. A semiconductor device comprising:
a gate wiring;
a wiring provided between adjacent pixel electrodes; and
a thin film transistor,
wherein the gate wiring is arranged so as to cross the wiring,
wherein a channel formation region of the thin film transistor is provided under the wiring,
wherein the channel formation region is provided at a position overlapping with the wiring at least partly,
wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a longitudinal direction of a region of the wiring,
wherein the region overlaps with the channel formation region, and
wherein a channel width of the channel formation region is longer than a channel length of the channel formation region.
9. The semiconductor device according to claim 8 , wherein a longitudinal direction of an impurity region connecting the channel formation regions is parallel to the channel width direction.
10. The semiconductor device according to claim 8 , wherein the channel formation region is at least one of an amorphous semiconductor and a polycrystalline semiconductor.
11. The semiconductor device according to claim 8 , wherein the thin film transistor includes a plurality of channel formation regions.
12. The semiconductor device according to claim 8 , wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the adjacent pixel electrodes, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the wiring.
13. A semiconductor device comprising:
a wiring provided between adjacent pixel electrodes; and
a thin film transistor,
wherein a channel formation region of the thin film transistor is provided under the wiring,
wherein the channel formation region is provided at a position overlapping with the wiring at least partly,
wherein the wiring is a signal line or a power supply line, and
wherein a channel width of the channel formation region is longer than a channel length of the channel formation region.
14. The semiconductor device according to claim 13 , wherein a longitudinal direction of an impurity region connecting the channel formation regions is parallel to a channel width direction.
15. The semiconductor device according to claim 13 , wherein the channel formation region is at least one of an amorphous semiconductor and a polycrystalline semiconductor.
16. The semiconductor device according to claim 13 , wherein the thin film transistor includes a plurality of channel formation regions.
17. The semiconductor device according to claim 13 , wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the adjacent pixel electrodes, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the wiring.
18. The semiconductor device according to claim 13 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a longitudinal direction of a region of the wiring which overlapping with the channel formation region.
19. The semiconductor device according to claim 13 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a direction in which current flows through the wiring.
20. A semiconductor device comprising:
a gate wiring;
a wiring provided between adjacent elements; and
a thin film transistor,
wherein the gate wiring is arranged so as to cross the wiring,
wherein a channel formation region of the thin film transistor is provided under the wiring,
wherein the channel formation region is provided at a position overlapping with the wiring at least partly, and
wherein a channel width of the channel formation region is longer than a channel length of the channel formation region.
21. The semiconductor device according to claim 20 , wherein a longitudinal direction of an impurity region connecting the channel formation regions is parallel to a channel width direction.
22. The semiconductor device according to claim 19 , wherein the channel formation region is at least one of an amorphous semiconductor and a polycrystalline semiconductor.
23. The semiconductor device according to claim 19 , wherein the thin film transistor includes a plurality of channel formation regions.
24. The semiconductor device according to claim 20 , wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the adjacent elements, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the wiring.
25. The semiconductor device according to claim 20 , wherein each of the elements is one selected from the group consisting of a light-emitting element, an organic memory, a photo diode, and a piezoelectric element.
26. The semiconductor device according to claim 20 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a longitudinal direction of a region of the wiring which overlapping with the channel formation region.
27. The semiconductor device according to claim 20 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a direction in which current flows through the wiring.
28. A semiconductor device comprising:
a gate wiring;
a wiring provided between adjacent elements; and
a thin film transistor,
wherein the gate wiring is arranged so as to cross the wiring,
wherein a channel formation region of the thin film transistor is provided under the wiring,
wherein the channel formation region is provided at a position overlapping with the wiring at least partly,
wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a longitudinal direction of a region of the wiring,
wherein the region overlaps with the channel formation region, and
wherein a channel width of the channel formation region is longer than a channel length of the channel formation region.
29. The semiconductor device according to claim 28 , wherein a longitudinal direction of an impurity region connecting the channel formation regions is parallel to the channel width direction.
30. The semiconductor device according to claim 28 , wherein the channel formation region is at least one of an amorphous semiconductor and a polycrystalline semiconductor.
31. The semiconductor device according to claim 28 , wherein the thin film transistor includes a plurality of channel formation regions.
32. The semiconductor device according to claim 28 , wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the adjacent elements, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the wiring.
33. The semiconductor device according to claim 28 , wherein each of the elements is one selected from the group consisting of a light-emitting element, an organic memory, a photo diode, and a piezoelectric element.
34. A semiconductor device comprising:
wiring provided between adjacent elements; and
a thin film transistor,
wherein a channel formation region of the thin film transistor is provided under the wiring,
wherein the channel formation region is provided at a position overlapping with the wiring at least partly,
wherein the wiring is a signal line or a power supply line, and
wherein a channel width of the channel formation region is longer than a channel length of the channel formation region.
35. The semiconductor device according to claim 34 , wherein a longitudinal direction of an impurity region connecting the channel formation regions is parallel to a channel width direction.
36. The semiconductor device according to claim 34 , wherein the channel formation region is at least one of an amorphous semiconductor and a polycrystalline semiconductor.
37. The semiconductor device according to claim 34 , wherein the thin film transistor includes a plurality of channel formation regions.
38. The semiconductor device according to claim 34 , wherein one of a source terminal and a drain terminal of the thin film transistor is connected to one of the adjacent elements, and
wherein the other of the source terminal and the drain terminal of the thin film transistor is connected to the wiring.
39. The semiconductor device according to claim 34 , wherein each of the elements is one selected from the group consisting of a light-emitting element, an organic memory, a photo diode, and a piezoelectric element.
40. The semiconductor device according to claim 34 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a longitudinal direction of a region of the wiring which overlapping with the channel formation region.
41. The semiconductor device according to claim 34 , wherein a channel width direction of the channel formation region is perpendicular to a channel length direction of the channel formation region in which current flows through the channel formation region and is parallel to a direction in which current flows through the wiring.