IP Library › Granted Patent US 7,863,928
Granted Patent B2
US 7,863,928 · App. 12/403,549 · Granted Jan 4, 2011

Data line termination circuit

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 7,863,928
App. No.
12/403,549
Granted
Jan 4, 2011
Kind
B2
Abstract

A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.

Claims (17)

1. A data line termination circuit comprising:

a swing-width sensing unit configured to sense a swing width of a voltage of a data line and to output a sensed signal according to the sensed swing width; and

a variable termination unit configured to adjust a termination resistance value of the data line according to the sensed signal, wherein the variable termination unit comprises:

a first termination unit configured to set a resistance value of the data line to a first termination resistance value according to the sensed signal; and

a second termination unit configured to set the resistance value of the data line to a second termination resistance value according to the sensed signal;

wherein the swing-width sensing unit is configured to compare the voltage of the data line with each of a plurality of reference voltages and to output the sensed signal having a logic level that is a first logic level or a second logic level, wherein the logic level is determined based upon whether the results of the comparison of each of the plurality of reference voltages with the voltage of the data line are the same,

wherein the swing-width sensing unit comprises:

a first comparator configured to compare the voltage of the data line with a first reference voltage;

a second comparator configured to compare the voltage of the data line with a second reference voltage;

a third comparator configured to compare the voltage of the data line with a third reference voltage; and

an encoder configured to encode outputs of the first to third comparators in order to output the sensed signal,

wherein the encoder is configured to output the sensed signal such that the logic level is the first logic level if the outputs of each of the first to third comparators have the same logic levels, and configured to output the sensed signal having the second logic level if the outputs of the first to third comparators all do not have the same logic level.

2. The data line termination circuit of claim 1 , wherein the second termination resistance value of the second termination unit is greater than the first termination resistance value of the first termination unit.

3. The data line termination circuit of claim 2 , wherein when the swing width sensing unit senses that the swing width of the voltage of the data line is greater than a predetermined swing width, the second termination unit is driven in order to reduce the swing width of the voltage of the data line.

4. The data line termination circuit of claim 1 , wherein the first termination resistance value of the first termination unit is greater than the second termination resistance value of the second termination unit.

5. The data line termination circuit of claim 4 , wherein when the swing width sensing unit senses that the swing width of the voltage of the data line is less than a predetermined swing width, the second termination unit is driven in order to increase the swing width of the voltage of the data line.

6. The data line termination circuit of claim 1 , wherein the variable termination unit further comprises a termination control unit which deactivates the first termination unit or the second termination unit in response to a termination control signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2009
From: KWON, YONG KEE; LEE, HYUNG DONG
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 022391/0402 →
Priority Claims (1)
KR 10-2008-0032994 · Apr 10, 2008 · national
Continuity (1)
Related Publication 20090256585A1 · Oct 15, 2009