Integrated DSP for a DC offset cancellation loop

1. A circuit, comprising:

an analog receiver; and

a feedback circuit comprising

an analog-to-digital converter coupled with the analog receiver to digitize an analog signal of the analog receiver;

a digital signal processor coupled with the analog-to-digital converter to generate a feedback signal to the analog

receiver, wherein the digital signal processor comprises a digital accumulator, and the digital accumulator comprises:

an adder;

a delay element coupled to an output of the adder; and

a digital loop filter coupled from an output of the delay element to an input of the adder; and

a digital-to-analog converter coupled with the digital signal processor to provide the feedback signal to the analog receiver, wherein the feedback signal reduces a direct current (DC) offset in the analog receiver.

2. The circuit of claim 1 , wherein the digital-to-analog converter comprises a sigma delta digital-to-analog converter.

3. The circuit of claim 1 , wherein the digital accumulator further comprises:

a gain controller coupled with the adder.

4. The circuit of claim 1 , wherein the feedback circuit further comprises:

a low pass filter coupled with the digital-to-analog converter to generate the feedback signal.

5. The circuit of claim 4 , wherein the low pass filter is implemented using integrated MOS capacitors; and the circuit is integrated on a single chip.

6. The circuit of claim 5 , wherein the circuit uses no external capacitor.

7. The circuit of claim 1 , wherein the analog receiver comprises a direct conversion receiver.

8. The circuit of claim 1 , wherein the analog receiver comprises a filter to reject signals modulated on carriers of channels other than a desired channel.

9. The circuit of claim 1 , wherein the feedback circuit further comprises a transconductance to generate the feedback signal.

10. The circuit of claim 4 , wherein the low pass filter comprises an integrated MOS capacitor.