Programming a normally single phase chalcogenide material for use as a memory of FPLA
A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.
1. A memory comprising:
a chalcogenide that is a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for thirty minutes or less; and
an array of programmably interconnected lines connected selectively by said chalcogenide.
2. The memory of claim 1 wherein said memory is a field programmable logic array.
3. The memory of claim 1 where said memory is a field programmable gate array.
4. The memory of claim 1 including a read circuit to apply a voltage between the threshold voltages of said states.
5. The memory of claim 1 including a programming circuit to apply pulses of different amplitude to program said different states.
6. The memory of claim 1 including a programming circuit to apply pulses with different fall times for said different states.
7. The memory of claim 1 including a cell with two memory elements in different states.
8. The memory of claim 1 wherein said chalcogenide material does not change phase.
9. The memory of claim 1 wherein said chalcogenide material includes 0 to 30% germanium, 0 to 60% tellurium, 11 to 40% arsenic, 0 to 42% selenium, and 5 to 15% antimony.
10. The memory of claim 1 including a common chalcogenide material for a plurality of cells.
11. The memory of claim 1 including a discrete chalcogenide material for each of a plurality of cells.
12. A method comprising:
forming an array of programmably interconnected lines; and
selectively connecting said lines by a chalcogenide being a generally amorphous chalcogenide layer that does not change to a generally crystalline phase when exposed to 200° C. for thirty minutes or less.
13. The method of claim 12 including forming a field programmable logic array.
14. The method of claim 12 including forming a field programmable gate array.
15. The method of claim 12 including using an Ovonic Threshold Switch as a memory cell in said memory.
16. The method of claim 12 including providing a cell with two memory elements programmed to opposite states.
17. The method of claim 12 including providing a higher magnitude pulse to program one state than the other.
18. The method of claim 12 including providing a first pulse with a first fall time to program a first state and a second pulse with a second fall time different than said first fall time to program a second state.
19. The method of claim 12 including reading the state of a memory cell by applying a reference voltage between the threshold voltages of said states.
20. The method of claim 12 including using a reference level to determine the state of a cell.
21. The method of claim 12 including using a non-disturbing pulse to return the threshold voltage to near its initial state.
22. The method of claim 12 including biasing deselected cells of an array of memory elements with a voltage that is greater than the difference in threshold voltages of bits in first and second states but less than the threshold voltage of a bit in the second state.
23. A method comprising:
forming an array of programmably interconnected lines;
selectively connecting said lines by a chalcogenide having a single phase with different thresholds; and
providing a first pulse with a first fall time to program a first state and a second pulse with a second fall time different than said first fall time to program a second state.
24. The method of claim 23 including reading the state of a memory cell by applying a reference voltage between the threshold voltages of said states.
25. The method of claim 23 including using a reference level to determine the state of a cell.
26. The method of claim 23 including using a non-disturbing pulse to return the threshold voltage to near its initial state.
27. The method of claim 23 including biasing deselected cells of an array of memory elements with a voltage that is greater than the difference in threshold voltages of bits in first and second states but less than the threshold voltage of a bit in the second state.
28. A method comprising:
forming an array of programmably interconnected lines; and
selectively connecting said lines by a chalcogenide having a single phase with different thresholds, including using a non-disturbing pulse to return the threshold voltage to near its initial state.
29. The method of claim 28 including biasing deselected cells of an array of memory elements with a voltage that is greater than the difference in threshold voltages of bits in first and second states but less than the threshold voltage of a bit in the second state.