Memory device and memory data read method
Provided are memory devices and memory data read methods. A method device may include: a multi-bit cell array; a decision unit that may detect threshold voltages of multi-bit cells of the multi-bit cell array to decide first data from the detected threshold voltages, using a first decision value; an error detector that may detect an error bit of the first data; and a determination unit that may determine whether the decision unit decides second data from the detected threshold voltages using a second decision value, based on a number of detected error bits, the second decision value being different from the first decision value. Through this, it is possible to reduce time spent for reading data stored in the multi-bit cell.
1. A memory device comprising:
a multi-bit cell array;
a decision unit configured to detects threshold voltages of multi-bit cells of the multi-bit cell array to decide first data from the detected threshold voltages using a first decision value;
an error detector configured to detects one or more error bits of the first data; and
a determination unit configured to determines whether the decision unit decides second data from the detected threshold voltages using a second decision value, based on a number of detected error bits, the second decision value being different from the first decision value,
wherein the first and second decision values are first and second sets of log likelihood ratios (LLR), respectively.
2. The memory device of claim 1 , wherein the determination unit is configured to selects the second decision value based on a pattern of the one or more detected error bits.
3. The memory device of claim 1 , wherein the determination unit is configured to adjust the first decision value based on at least one of floating gate coupling and a charge loss mechanism to form the second decision value.
4. The memory device of claim 1 , wherein the decision unit is configured to performs hard-decision for the first data from the detected threshold voltages, using the first decision value.
5. The memory device of claim 1 , wherein
the decision unit is configured to performs soft-decision for the first data from the detected threshold voltages, using the first decision value.
6. The memory device of claim 1 , wherein the determination unit is configured to determines that the decision unit decides the second data from the detected threshold voltages using the second decision value if the number of detected error bits is greater than an error correction range.
7. The memory device of claim 1 , wherein:
if the determination unit identifies a multi-bit cell storing a detected error bit from among the one or more detected error bits,
the decision unit is configured to decides the second data from a detected threshold voltage of the identified multi-bit cell, using the second decision value.
8. A method of reading data from a memory, comprising:
detecting threshold voltages of multi-bit cells of a multi-bit cell array;
deciding first data from the detected threshold voltages using a first decision value;
detecting one or more error bits of the first data; and
determining whether to decide second data from the detected threshold voltages using a second decision value based on a number of detected error bits, the second decision value being different from the first decision value,
wherein the first and second decision values are first and second sets of log likelihood ratios (LLR), respectively.
9. The method of claim 8 , further comprising:
selecting the second decision value based on a pattern of the one or more detected error bits.
10. The method of claim 8 , wherein when the number of detected error bits is greater than an error correction range, the determining determines the second data is decided from the detected threshold voltages using the second decision value.
11. The method of claim 8 , further comprising:
identifying a multi-bit cell storing a detected error bit from among the one or more detected error bits; and
deciding the second data from a detected threshold voltage of the identified multi-bit cell, using the second decision value.
12. The method of claim 8 , further comprising:
adjusting the first decision value when the number of detected error bits is greater than a reference value.
13. A computer-readable recording medium storing a program for implementing the method of claim 8 .
14. The memory device of claim 1 , wherein the first and second sets of LLRs each include a log likelihood ratio corresponding to each possible data value for data that can be stored in a cell from among the multi-bit cell array.
15. The method of claim 8 , wherein the first and second sets of LLRs each include a log likelihood ratio corresponding to each possible data value for data that can be stored in a cell from among the multi-bit cell array.