Static power reduction for midpoint-terminated busses
View Patent ↗A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.
1. A method for reducing power consumption in a computer memory system including a memory bus, an array of memory devices, a driver subsystem, and a termination voltage source, wherein the memory bus includes a multitude of bus lines connected to the memory devices, the driving subsystem is connected to the bus lines for charging the bus lines to high or low states, and the termination voltage source is connected to the bus lines through termination resistors, and wherein the memory bus has defined periods of inactivity, the method comprising the steps of:
providing a register for storing a series of predetermined register bits for setting the bus lines to predetermined states during said periods of inactivity, each of said predetermined register bits being associated with one of the bus lines, and identifying one of said high or low states for said associated bus line; and
during said periods of inactivity of the memory bus, driving at least some of the bus lines to high or low states in accordance with the predetermined register bits to reduce the drive current supplied by the termination voltage source during said periods of inactivity.
2. A method according to claim 1 , wherein at least some of the register bits are programmable.
3. A method according to claim 1 , comprising the further step of setting an additional group of register bits to defined levels in order to achieve a given memory operation.
4. A method according to claim 1 , comprising the further step of hardcoding all of said register bits to defined levels in order to achieve a given memory operation with minimal termination voltage supply current.
5. A method according to claim 1 , wherein the driving step includes the step of:
identifying one or more of the bus lines that do not affect memory control operation during periods of inactivity of the memory bus; and
driving said one or more identified bus lines to reduce the drive current supplied by the termination voltage source.
6. A method according to claim 1 , comprising the further step of setting said register bits to achieve a given ratio of bus lines in the high state vs. the low state.
7. A method according to claim 1 , comprising the further step of using the register bits to initialize long-term operation of the memory devices during power-on and reset periods of the memory system.
8. A control system according to claim 7 , wherein at least some of the register bits are programmable.
9. A control system according to claim 7 , wherein an additional group of register bits are set to defined levels in order to achieve a given memory operation.
10. A control system according to claim 7 , wherein all of said register bits are hardcoded to defined levels in order to achieve a given memory operation with minimal termination voltage supply current.
11. A control system according to claim 7 , wherein:
the memory system identifies one or more of the bus lines that do not affect memory control operation during periods of inactivity of the memory bus; and
during said periods of inactivity of the memory bus, the driving subsystem drives said one or more identified bus lines to reduce the drive current supplied by the termination voltage source.
12. A control system according to claim 7 , wherein said register bits are set to achieves a given ratio of bus lines in the high state vs. the low state, and said given ratio is determined based on at least one of the voltage of the termination voltage source and the ratio of pullup and pulldown drive strengths of the address and control bus drivers.
13. A control system according to claim 7 , comprising the further step of using the register bits to initialize long-term operation of the memory devices during power-on and reset periods of the memory system.
14. A method for reducing power consumption in a computer memory system including a memory bus, an array of memory devices, a driver subsystem, and a termination voltage source, wherein the memory bus includes a multitude of bus lines connected to the memory devices, the driving subsystem is connected to the bus lines for charging the bus lines to high or low states, and the termination voltage source is connected to the bus lines through termination resistors, and wherein the memory bus has defined periods of inactivity, the method comprising the steps of:
providing a register for storing a series of register bits, each of said register bits being associated with one of the bus lines, and identifying one of said high or low states for said associated bus line;
during periods of inactivity of the memory bus, driving at least some of the bus lines to high or low states in accordance with the register bits to reduce the drive current supplied by the termination voltage source; and
setting said register bits to achieve a given ratio of bus lines in the high states vs. the low state, and wherein said given ratio is determined based on at least one of the voltage of the termination voltage source and the ratio of pullup and pulldown drive strengths of the address and control bus drivers.
15. A control system for reducing power consumption in a computer memory system including a memory bus, an array of memory devices, a driver subsystem, and a termination voltage source, wherein the memory bus includes a multitude of bus lines connected to the memory devices, the driving subsystem is connected to the bus lines for charging the bus lines to high or low states, and the termination voltage source is connected to the bus lines through termination resistors, and wherein the memory bus has defined periods of inactivity, the control system comprising:
a register for storing a series of predetermined register bits for setting the bus lines to predetermined states during said periods of inactivity, each of said predetermined register bits being associated with one of the bus lines, and identifying one of said high or low states for said associated bus line; and
wherein, during said periods of inactivity of the memory bus, the driver subsystem drives at least some of the bus lines to high or low states in accordance with the predetermined register bits to reduce the drive current supplied by the termination voltage source during said periods of inactivity.
16. A computer readable storage medium, tangibly embodying a program of instructions executable by the computer to perform method steps for reducing power consumption in a computer memory system including a memory bus, an array of memory devices, a driver subsystem, and a termination voltage source, wherein the memory bus includes a multitude of bus lines connected to the bus lines through termination resistors, and wherein the memory bus has defined periods of inactivity, the method steps comprising:
accessing a register for storing a series of predetermined register bits for setting the bus lines to predetermined states during said periods of inactivity, each of said register bits being associated with one of the bus lines, and identifying one of said high or low states for said associated bus line; and
during said periods of inactivity of the memory bus, driving at least some of the bus lines to high or low states in accordance with the predetermined register bits to reduce the drive current supplied by the midpoint voltage source during said periods of inactivity.
17. A computer readable storage medium according to claim 16 , wherein at least some of the register bits are programmable.
18. A computer readable storage medium according to claim 16 , wherein the driving step includes the steps of:
identifying one or more of the bus lines that do not affect memory control operation during periods of inactivity of the memory bus; and
driving said one or more identified bus lines to reduce the drive current supplied by the termination voltage source.
19. A computer readable storage medium according to claim 16 , wherein the method steps comprise the further step of setting said register bits to achieve a given ratio of bus lines in the high state vs. the low state.
20. A computer readable storage medium according to claim 19 , wherein said given ratio is determined based on at least one of the voltage of the termination voltage source and the ratio of pullup and pulldown drive strengths of the address and control bus drivers.