IP Library › Granted Patent US 7,879,679
Granted Patent B2
US 7,879,679 · App. 12/059,497 · Granted Feb 1, 2011

Electronic component manufacturing method

Assignee: STMicroelectronics Crolles 2 SAS
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Quick Facts
Patent No.
US 7,879,679
App. No.
12/059,497
Granted
Feb 1, 2011
Kind
B2
Abstract

A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.

Claims (33)

1. A method for manufacturing an electronic component on a semiconductor substrate, comprising:

forming at least one opening in the substrate;

forming in a bottom and on walls of the opening and on the substrate, an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and with respect to the substrate;

trimming the layer portions of the first material and of the second material which are not located in said opening;

selectively etching a portion of the first material to obtain trenches; and

filling the trenches with at least one third material.

2. The method of claim 1 , wherein the third material is deposited by a so-called ALD deposition method.

3. The method of claim 1 , wherein the substrate is made of silicon, the first material is silicon-germanium, the second material is silicon, and wherein the structure gathering the substrate, the first material, and the second material is doped of a first conductivity type down to a depth greater than the depth of the opening.

4. The method of claim 3 , wherein the silicon-germanium layers and the silicon layers are formed by epitaxy.

5. The method of claim 4 , wherein the filling with the third material comprises:

depositing an insulating layer in the bottom and on the walls of the trenches and on the substrate;

depositing a conductive layer on the insulating layer; and

forming a first contact connected to the conductive layer and a second contact connected to the substrate to form a capacitor between the first contact and the second contact.

6. The method of claim 4 , wherein the filling with the third material comprises:

depositing at least one doped semiconductor layer of a second conductivity type; and

forming a first contact connected to the doped semiconductor layer and a second contact connected to the substrate to form a diode between the first contact and the second contact.

7. A method for manufacturing an electronic component on a semiconductor substrate, comprising:

forming at least one opening in the substrate;

forming in a bottom and on walls of the opening and on the substrate, an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and with respect to the substrate;

trimming the layer portions of the first material and of the second material which are not located in said opening;

selectively etching a portion of the first material to obtain trenches; and

filling the trenches with at least one third material, wherein the filling with the third material comprises:

depositing an insulating layer in the bottom and on the walls of the trenches and on the substrate;

depositing a conductive layer on the insulating layer; and

forming a first contact connected to the conductive layer and a second contact connected to the substrate to form a capacitor between the first contact and the second contact.

8. A method for manufacturing an electronic component on a semiconductor substrate, comprising:

forming at least one opening in the substrate;

forming in a bottom and on walls of the opening and on the substrate, an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and with respect to the substrate;

trimming the layer portions of the first material and of the second material which are not located in said opening;

selectively etching a portion of the first material to obtain trenches; and

filling the trenches with at least one third material, wherein the filling with the third material comprises:

depositing at least one doped semiconductor layer of a second conductivity type; and

forming a first contact connected to the doped semiconductor layer and a second contact connected to the substrate to form a diode between the first contact and the second contact.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2008
From: KERMARREC, OLIVER; BENSAHEL, DANIEL; CAMPIDELLI, YVES
To: STMICROELECTRONICS CROLLES 2 SAS
Reel/Frame 020849/0026 →
Priority Claims (1)
FR 07 54201 · Apr 2, 2007 · national
Continuity (1)
Related Publication 20080239625A1 · Oct 2, 2008