Granted Patent B1

US 7,889,750 · App. 11/324,205 · Granted Feb 15, 2011

Assignee: Extreme Networks, Inc.

Abstract

Claims (55)

1. In a packet processing system, a method comprising:

implementing a processing pipeline having a fixed number of processing cycles, the fixed number of processing cycles to be applied to each packet through the pipeline as a default fixed number of processing cycles;

maintaining a count of a number of processing cycles performed or remaining for each packet relative to the default fixed number of processing cycles, wherein the count of the number of processing cycles performed or remaining for each packet is maintained within a FIFO (First In First Out) buffer of the packet processing system as state data within a pointer to the corresponding packet maintained in a separate and distinct FIFO buffer having the corresponding packet buffered therein;

prior to completion of the default fixed number of processing cycles for each packet:

determining whether processing is complete for the packet or whether extended processing is required for the packet,

setting a DONE bit for the packet when processing is complete for the packet prior to completion of the default fixed number of processing cycles, and

setting an extension bit when extended processing is required for the packet in excess of the default fixed number of processing cycles for the packet;

exiting each packet from the processing pipeline having its respective DONE bit is set;

allocating excess cycles in the processing pipeline for each packet exited from the processing pipeline due to having its respective DONE bit set, to one or more packets having their respective extension bit set indicating extended processing is required for the one or more packets, wherein a quantity of excess cycles allocated corresponds to the difference between the count of the number of processing cycles performed or remaining for each packet exited from the processing pipeline due to having its respective DONE bit relative to the default fixed number of processing cycles; and

applying the excess cycles in the processing pipeline to the extended processing required for each packet having its respective extension bit set, wherein the excess cycles are applied to each packet having its respective extension bit set through a subsequent cycle of the same processing pipeline.

2. The method of claim 1 wherein the default state of the extension bit is off and wherein the default state of the DONE bit is “off.”

3. The method of claim 1 , further comprising incrementing the count if the extension bit is set to the “off” state, and having each packet exited from the processing pipeline once the count equals or exceeds the default fixed number of processing cycles.

4. The method of claim 1 , further comprising updating the count of the number of processing cycles performed or remaining for each packet by decrementing the count, when the count indicates a number of processing cycles remaining for each packet, and having the packet exited from the pipeline once the count is less than or equal to zero and the extension bit is off.

5. The method of claim 1 , further comprising:

having each packet exited from the pipeline once the done bit is set to the “on” state, even if the count of the number of processing cycles performed or remaining indicates the number of processing cycles the packet has undergone is less than the default fixed number of processing cycles for the processing pipeline.

6. The method of claim 5 wherein the default “off” state of the done bit is a logical “0” and the “on” state of that bit is a logical “1.”

7. The method of claim 5 wherein the default “off” state of the done bit is a logical “1” and the “on” state of that bit is a logical “0.”

8. The method of claim 1 wherein the packet processing system is in a router, switch, or combination router/switch.

9. The method of claim 8 wherein the packet processing system is for making a classification and forwarding decision for a packet.

10. The method of claim 8 wherein the packet processing system is implemented through ASIC technology on one or more integrated circuit chips.

11. A packet processing system comprising:

a processor;

a plurality of commands, instructions, and/or state transitions;

wherein the processor of the packet processing system to execute the plurality of commands, instructions, and/or state transitions causing the packet processing system to perform a method comprising:

implementing a processing pipeline having a fixed number of processing cycles, the fixed number of processing cycles to be applied to each packet through the pipeline as a default fixed number of processing cycles;

maintaining a count of a number of processing cycles performed or remaining for each packet relative to the default fixed number of processing cycles, wherein the count of the number of processing cycles performed or remaining for each packet is maintained within a FIFO (First In First Out) buffer of the packet processing system as state data within a pointer to the corresponding packet maintained in a separate and distinct FIFO buffer having the corresponding packet buffered therein;

prior to completion of the default fixed number of processing cycles for each packet:

determining whether processing is complete for the packet or whether extended processing is required for the packet,

setting a DONE bit for the packet when processing is complete for the packet prior to completion of the default fixed number of processing cycles, and

setting an extension bit when extended processing is required for the packet in excess of the default fixed number of processing cycles for the packet;

exiting each packet from the processing pipeline having its respective DONE bit is set;

allocating excess cycles in the processing pipeline for each packet exited from the processing pipeline due to having its respective DONE bit set, to one or more packets having their respective extension bit set indicating extended processing is required for the one or more packets; and

applying the excess cycles in the processing pipeline to the extended processing required for each packet having its respective extension bit set, wherein the excess cycles are applied to each packet having its respective extension bit set through a subsequent cycle of the same processing pipeline.

12. The packet processing system of claim 11 , wherein the method performed further comprises:

updating the count of the number of processing cycles performed or remaining for each packet by decrementing the count, when the count indicates a number of processing cycles remaining for each packet; and

exiting the packet from the pipeline once the count is less than or equal to zero and the extension bit is off.

13. The packet processing system of claim 11 , wherein the method performed further comprises:

exiting each packet from the pipeline once the done bit is set to the “on” state, even if the count of the number of processing cycles performed or remaining indicates the number of processing cycles the packet has undergone is less than the default fixed number of processing cycles for the processing pipeline.

14. A packet processing system comprising:

a packet processor to implement a processing pipeline having a fixed number of processing cycles, the fixed number of processing cycles to be applied to each packet through the pipeline as a default fixed number of processing cycles wherein the packet processor is to:

maintain a count of a number of processing cycles performed or remaining for each packet relative to the default fixed number of processing cycles, wherein the count of the number of processing cycles performed or remaining for each packet is maintained within a FIFO (First In First Out) buffer of the packet processing system as state data within a pointer to the corresponding packet maintained in a separate and distinct FIFO buffer having the corresponding packet buffered therein;

determine, prior to completion of the default fixed number of processing cycles for each packet:

whether processing is complete for the packet or whether extended processing is required for the packet,

set a DONE bit for the packet when processing is complete for the packet prior to completion of the default fixed number of processing cycles, and

set an extension bit when extended processing is required for the packet in excess of the default fixed number of processing cycles for the packet;

wherein the packet processor is to further:

exit each packet from the processing pipeline having its respective DONE bit is set;

allocate excess cycles in the processing pipeline for each packet exited from the processing pipeline due to having its respective DONE bit set, to one or more packets having their respective extension bit set indicating extended processing is required for the one or more packets; and

apply the excess cycles in the processing pipeline to the extended processing required for each packet having its respective extension bit set, wherein the excess cycles are applied to each packet having its respective extension bit set through a subsequent cycle of the same processing pipeline.

15. The packet processing system of claim 14 , wherein the packet processor is to further increment the count if the extension bit is set to the “off” state, and having each packet exited from the processing pipeline once the count equals or exceeds the default fixed number of processing cycles.

16. The packet processing system of claim 14 , wherein the packet processor is to further:

update the count of the number of processing cycles performed or remaining for each packet by decrementing the count, when the count indicates a number of processing cycles remaining for each packet, and

exit the packet from the pipeline once the count is less than or equal to zero and the extension bit is off.

17. The packet processing system of claim 14 , wherein the packet processor is to further:

exit each packet from the pipeline once the done bit is set to the “on” state, even if the count of the number of processing cycles performed or remaining indicates the number of processing cycles the packet has undergone is less than the default fixed number of processing cycles for the processing pipeline.

Assignments (10)

Continuity (1)