IP Library › Granted Patent US 7,900,033
Granted Patent B2
US 7,900,033 · App. 11/768,391 · Granted Mar 1, 2011

Firmware processing for operating system panic data

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,900,033
App. No.
11/768,391
Granted
Mar 1, 2011
Kind
B2
Abstract

A processor includes firmware and at least one instance of an operating system (OS). When the OS encounters an unrecoverable error (a “panic”), data regarding the error is pushed to the firmware via capsule services, rather than immediately being displayed to the screen via legacy video INT10h services. The panic data may be provided to the OS and displayed by the OS after a reset. Other embodiments are also described and claimed.

Claims (52)

1. A system, comprising:

a processor coupled with a firmware memory to store a capsule logic module; and

a memory coupled to the processor, the memory to store an operating system;

wherein the capsule logic module is further to receive panic data from the operating system responsive to detection of an unrecoverable error by the operating system.

2. The system of claim 1 , wherein:

the panic data is run-time data.

3. The system of claim 1 , wherein:

said firmware memory is a flash memory.

4. The system of claim 1 , wherein:

said memory further comprises a dynamic random access memory module.

5. The system of claim 1 , wherein:

said firmware memory is further to store logic to provide at least a portion of the panic data in a persistent storage location that is accessible to the operating system after reset of the processor.

6. The system of claim 1 , wherein:

said system further comprises a second processor coupled to a display screen; and

said firmware memory is further to store logic to provide at least a portion of the panic data to the second processor for display on the display screen after reset of the processor.

7. The system of claim 6 , wherein:

said second processor is manageability engine.

8. The system of claim 1 , wherein:

said firmware memory is further to store logic to provide at least a portion of the panic data to an error log after reset.

9. The system of claim 1 , wherein:

said firmware memory is further to store logic to provide at least a portion of the panic data to a script.

10. The system of claim 5 , further comprising:

a network connection to support out-of-band communication with the second processor.

11. A method comprising:

receiving from an operating system, via a call to a capsule function, runtime data related to an unrecoverable error;

storing the runtime data in a nonvolatile memory location accessible by the operating system after a system reset;

performing system reset initialization processing; and

re-booting the operating system.

12. The method of claim 11 , wherein:

said receiving, storing, performing and re-booting are performed prior to any display of the runtime data to a display screen.

13. The method of claim 11 , further comprising:

performing pre-boot processing of the panic data before said re-booting.

14. The method of claim 13 , wherein:

said pre-boot processing further comprises providing at least a portion of said panic data to a diagnostic script.

15. The method of claim 13 , wherein:

said pre-boot processing further comprises providing at least a portion of said panic data for display on a display screen.

16. The method of claim 13 , wherein:

said pre-boot processing further comprises providing at least a portion of said panic data to an error log.

17. An article comprising:

a tangible storage medium having a plurality of machine accessible instructions;

wherein, when the instructions are executed by a processor, the instructions provide for:

receiving a function call for a capsule payload related to an unrecoverable error encountered during execution of an operating system;

storing the payload in a persistent memory location that is accessible by the operating system after a system reset; and

re-booting the operating system.

18. The article of claim 17 , wherein said instructions further provide for:

performing system reset initialization processing.

19. The article of claim 17 , wherein said instructions further provide for:

displaying at least a portion of the capsule payload to a display screen.

20. The article of claim 19 , wherein said instructions further provide for:

displaying at least a portion of the capsule payload to a display screen without invoking a Int 10h facility.

21. The article of claim 19 , wherein said instructions further provide for:

displaying at least a portion of the capsule payload to a display screen via an UEFI-compliant display driver.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2009
From: ROTHMAN, MICHAEL A.; ZIMMER, VINCENT J.
To: INTEL CORPORATION
Reel/Frame 022724/0936 →
Continuity (1)
Related Publication 20090006827A1 · Jan 1, 2009