Semiconductor package and method for manufacturing the same

1. A semiconductor package comprising:

a carrier;

a chip disposed on the carrier and electrically connected to the carrier;

a stiffener made of a ceramic material disposed around the chip, directly contacting the carrier, and mounted on the carrier, wherein the stiffener comprises a through opening and the chip is located within the through opening; and

an encapsulant adapted to seal the chip and cover the stiffener.

2. The semiconductor package as claimed in claim 1 , wherein the stiffener includes a surface contacting the carrier, and the surface has a groove.

3. The semiconductor package as claimed in claim 2 , wherein the cross-section of the groove is triangular.

4. The semiconductor package as claimed in claim 2 , wherein the cross-section of the groove is rectangular.

5. The semiconductor package as claimed in claim 1 , wherein the carrier comprises at least one first positioning hole, the stiffener comprises at least one second positioning hole, and the first positioning hole is corresponding to the second positioning hole.

6. The semiconductor package as claimed in claim 1 , wherein a height of the stiffener is smaller than that of the chip.

7. A method for manufacturing semiconductor packages comprising the following steps of:

providing a carrier, wherein the carrier includes at least one first positioning hole;

disposing at least one chip on the carrier;

disposing a stiffener on the carrier, wherein the stiffener directly contacting the carrier, the stiffener is disposed around the chip, and the stiffener comprises at least one second positioning hole corresponding to the first positioning hole;

temporarily mounting the stiffener on the carrier by an alignment step; and

sealing the chip and the stiffener and mounting the stiffener on the carrier by an encapsulant so as to form at least one semiconductor package.

8. The method as claimed in claim 7 , further comprising the following step of:

sawing the encapsulant, the carrier and the stiffener, thereby singularizing the semiconductor package, wherein the semiconductor package still include the stiffener.

9. The method as claimed in claim 7 , further comprising the following step of:

sawing the encapsulant and the carrier, thereby singularizing the semiconductor package, wherein the semiconductor package does not include the stiffener.

10. The method as claimed in claim 7 , wherein the alignment step comprises the following processes of: providing a tool for aligning the second positioning hole of the stiffener with the first positioning hole of the carrier, and temporarily mounting the stiffener on the carrier.

11. The method as claimed in claim 10 , wherein the alignment step further comprises the following process of: removing the tool.

12. The method as claimed in claim 11 , wherein the tool comprises an upper mold and a lower mold.

13. The method as claimed in claim 12 , wherein the lower mold comprises a positioning pin for inserting the second positioning hole and the first positioning hole, thereby aligning the second positioning hole of the stiffener with the first positioning hole of the carrier.

14. The method as claimed in claim 12 , wherein the upper mold is adapted to press the stiffener and the carrier, thereby temporarily mounting the stiffener on the carrier.

15. The method as claimed in claim 7 , wherein the encapsulation step comprises the process of molding the encapsulant.

16. The method as claimed in claim 15 , wherein the stiffener is mounted on carrier by an attaching force of the encapsulant.

17. The method as claimed in claim 7 , wherein the stiffener includes a surface contacting the carrier, and the surface has a groove.

18. The method as claimed in claim 7 , wherein a height of the stiffener is smaller than that of the chip.

19. The semiconductor package as claimed in claim 1 , further comprising a plurality of bumps disposed between the chip and the carrier for electrically connecting the chip to the carrier.