IP Library › Granted Patent US 7,903,813
Granted Patent B2
US 7,903,813 · App. 11/905,468 · Granted Mar 8, 2011

Stream cipher encryption application accelerator and methods thereof

Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 7,903,813
App. No.
11/905,468
Granted
Mar 8, 2011
Kind
B2
Abstract

A system for encrypting and decrypting data formed of a number of bytes using the ARCFOUR encryption algorithm is disclosed. The system includes a system bus and an encryption accelerator arranged to execute the encryption algorithm coupled to the system bus. A system memory coupled to the system bus arranged to store a secret key array associated with the data and a central processing unit coupled to the system bus wherein encryption accelerator uses substantially no central processing unit resources to execute the encryption algorithm.

Claims (24)

1. A method for performing an RC4 stream cipher on an input data stream in an encryption accelerator, comprising:

initializing an RC4 substitution box in a state memory, wherein the substitution box initialization includes:

storing an incrementing pattern of values in incrementing memory locations in the state memory, and

shuffling, upon direction of a state machine within the encryption accelerator, the values among the memory locations in the state memory based on a received key array having a plurality of portions, wherein the shuffling is performed with receipt of each portion of the key array by the encryption accelerator whereby an initial shuffled pattern of substitution values is generated via hardware and stored in a plurality of memory locations in the state memory; and

generating, upon direction of the state machine, a random byte using the shuffled substitution box according to an RC4 cipher operation,

wherein no central processing unit resources are invoked to perform the shuffling and generating components of the RC4 stream cipher.

2. The method of claim 1 , wherein initializing the RC4 substitution box further comprises:

receiving the key array from a system memory via an interface to an external to the encryption accelerator.

3. The method of claim 1 , further comprising:

combining the random byte with a portion of an input data stream received in the encryption accelerator to generate an encrypted data input byte.

4. The method of claim 1 , further comprising:

receiving an interrupt;

storing a state of the state memory for the first input data stream in an external memory; and

performing an RC4 stream cipher on a second input data stream.

5. The method of claim 4 , further comprising:

restoring the state of first input data stream in the state memory; and

resuming the RC4 stream cipher on the first input data stream.

6. A system performing an RC4 stream cipher on an input data stream:

a system memory arranged to store a key array associated with the input data stream; and

an encryption accelerator having a state machine and a state memory, wherein the encryption accelerator configured to execute the RC4 stream cipher upon direction of the state machine including performing an RC4 shuffling operation using a portion of the key array received from the system memory,

wherein no central processing unit resources are invoked to perform the shuffling operation of the RC4 stream cipher, and

wherein the encryption accelerator is further configured to perform the RC4 shuffling operation concurrently with the receipt of each portion of the key array by the encryption accelerator whereby an initial shuffled pattern of substitution values is generated via hardware and stored in a plurality of memory locations in the state memory.

7. The system of claim 6 , wherein the encryption accelerator is configured to store a current state of the state memory in the external system memory upon receipt of an interrupt request.

8. The system of claim 7 , wherein the encryption accelerator is selectively operable in an Initial Mode and a Continuation mode wherein the Initial Mode the system operates in a sequential manner whereas in the continuation mode the state memory is reloaded with the stored state from the external system memory.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2007
From: DUVAL, DONALD E.
To: BROADCOM CORPORATION
Reel/Frame 019956/0037 →
Continuity (3)
Continuation 09916557 · Jul 26, 2001
Provisional Application 60235190 · Sep 25, 2000
Related Publication 20080107260A1 · May 8, 2008