System for optimizing the performance and reliability of a storage controller cache offload circuit
A method for offloading a cache memory is disclosed. The method generally includes the steps of (A) reading all of a plurality of cache lines from the cache memory in response to an assertion of a signal to offload of the cache memory, (B) generating a plurality of blocks by dividing the cache lines in accordance with a RAID configuration and (C) writing the blocks among a plurality of nonvolatile memories in the RAID configuration, wherein each of the nonvolatile memories has a write bandwidth less than a read bandwidth of the cache memory.
1. A method for offloading a cache memory, comprising the steps of:
(A) exchanging a plurality of cache lines between said cache memory and a main memory directly through a controller, said main memory and said cache memory being volatile;
(B) exchanging data between a processor and said main memory through said controller without passing through said cache memory;
(C) buffering all of said cache lines from said cache memory in said controller in response to an assertion of a signal that indicates a loss of power;
(D) generating a plurality of blocks in said controller by dividing said cache lines as buffered in accordance with a RAID configuration; and
(E) writing said blocks from said controller directly to a plurality of nonvolatile memories in said RAID configuration after said loss of power, wherein each of said nonvolatile memories has (i) a write bandwidth less than a read bandwidth of said cache memory and (ii) a different independent path to said controller to convey said blocks.
2. The method according to claim 1 , wherein at least two of said blocks are written substantially simultaneously to said nonvolatile memories.
3. The method according to claim 1 , further comprising the step of:
generating a plurality of stripes by striping said blocks, wherein each of said stripes includes at most a subset of a corresponding one of said blocks.
4. The method according to claim 3 , wherein step (E) comprises the sub-step of:
writing (i) said stripes and (ii) a parity of said stripes of a same rank among said nonvolatile memories.
5. The method according to claim 4 , wherein at least two of said stripes are written substantially simultaneously to said nonvolatile memories.
6. The method according to claim 1 , wherein (i) said assertion of said signal indicates said loss of power flowing into a power circuit and (ii) said power circuit is configured to power said controller, said cache memory and said nonvolatile memories after said loss of power.
7. The method according to claim 1 , wherein (i) each of said nonvolatile memories has a first storage capacity, (ii) said cache memory has a second storage capacity and (iii) a total of said first storage capacity is at least as great as said second storage capacity.
8. The method according to claim 1 , wherein a total of said write bandwidths of said nonvolatile memories is at least as great as said read bandwidth of said cache memory.
9. The method according to claim 1 , wherein said cache lines are read from said cache memory at a first bandwidth proximate said read bandwidth of said cache memory.
10. The method according to claim 9 , wherein said blocks are written to said nonvolatile memories at a second bandwidth proximate said write bandwidth of said nonvolatile memories.
11. A system comprising:
a cache memory having a read bandwidth and configured to store a plurality of cache lines, said cache memory being volatile;
a plurality of nonvolatile memories each having a write bandwidth less than said read bandwidth;
a controller configured to (i) buffer all of said cache lines received from said cache memory in response to an assertion of a signal that indicates a loss of power, (ii) generate a plurality of blocks by dividing said cache lines as buffered in accordance with a RAID configuration and (iii) write said blocks directly to said nonvolatile memories in said RAID configuration after said loss of power, wherein each of said nonvolatile memories has a different independent path to said controller to convey said blocks;
a main memory configured to exchange said cache lines with said cache memory directly through said controller, said main memory being volatile; and
a processor configured to exchange first data with said main memory through said controller without passing through said cache memory.
12. The system according to claim 11 , wherein at least two of said blocks are written substantially simultaneously to said nonvolatile memories.
13. The system according to claim 11 , wherein processor is further configured to exchange second data with said cache memory through said controller.
14. The system according to claim 11 , further comprising a power circuit configured to assert said signal.
15. The system according to claim 14 , wherein said assertion of said signal indicates said loss of power flowing into said power circuit and (ii) said power circuit is further configured to power said controller, said cache memory and said nonvolatile memories after said loss of power.
16. The system according to claim 14 , wherein said power circuit comprises at least one of a super-capacitor and an ultra-capacitor to deliver power after deactivation of a source power.
17. The system according to claim 11 , further comprising at least four slots, each of said slots configured to connect to one of said nonvolatile memories.
18. The system according to claim 17 , wherein at least one of said slots is empty in at least one configuration of said system.
19. The system according to claim 17 , wherein said RAID configuration comprises one of (i) a RAID 0 configuration, (ii) a RAID 1 configuration and (iii) a RAID 5 configuration.
20. The system according to claim 11 , wherein (i) said controller is further configured to generate a plurality of stripes by striping said blocks and (ii) each of said stripes includes at most a subset of a corresponding one of said blocks.
21. A system comprising:
means for volatile storage having a read bandwidth and configured to store of a plurality of cache lines;
a plurality of means for nonvolatile storage each having a write bandwidth less than said read bandwidth;
means for controlling comprising (i) buffering all of said cache lines received from said means for volatile storage in response to an assertion of a signal that indicates a loss of power, (ii) generating a plurality of blocks by dividing said cache lines as buffered in accordance with a RAID configuration and (iii) writing said blocks directly to said means for nonvolatile storage in said RAID configuration after said loss of power, wherein each of said means for nonvolatile storage has a different independent path to said means for controlling to convey said blocks;
means for main memory configured to exchange said cache lines with said means for volatile storage directly through said means for controlling; and
means for processing configured to exchange data with said means for main memory through said means for controlling without passing through said means for volatile storage.