Demodulator
According to one embodiment, a threshold adjusting apparatus for a clocked comparator, the clocked comparator comparing an input signal with a threshold in accordance with a clock, the threshold adjusting apparatus comprises an output detection module configured to detect an output from the clocked comparator with the threshold while changing the threshold and a setting module configured to set the threshold when the output detection module detects a change in the output from the clocked comparator as an adjusted threshold.
1. An amplitude shift keying demodulator comprising:
a rectifier circuit configured to supply a bias voltage at a predetermined timing and comprising a bias circuit configured to output a direct current voltage, a first MOS transistor in which the direct current voltage is applied between a gate terminal and a source terminal, a second MOS transistor in which the direct current voltage is applied between a gate terminal and a source terminal and a drain terminal is connected to the source terminal of the first MOS transistor, and a coupling capacitor having an end connected to the source terminal of the first MOS transistor and another end from which an alternate current signal is input; and
a clocked comparator configured to compare an input signal rectified by the rectifier circuit with a threshold at a timing different from the predetermined timing and to output a binary signal.
2. The amplitude shift keying demodulator of claim 1 , wherein the rectifier circuit operates in synchronization with a rising edge of a clock signal, and the comparator operates in synchronization with a falling edge of the clock signal.
3. The amplitude shift keying demodulator of claim 1 , wherein the clocked comparator comprises a dynamic latch and a set-reset latch.
4. The amplitude shift keying demodulator of claim 3 , wherein the dynamic latch comprises an input transistor section to which the input signal and a threshold are input, a positive feedback section which operates in accordance with the clock signal, and a load capacitance section comprising a fixed capacitance and a variable capacitance, and a threshold of the clocked comparator is controlled by changing the variable capacitance.
5. The amplitude shift keying modulator of claim 1 , further comprising a threshold control module configured to detect a DC offset voltage of the clocked comparator and to set the DC offset voltage as the threshold of the clocked comparator.
6. The amplitude shift keying modulator of claim 5 , further comprising an analog conversion module configured to perform analog conversion on an output from the threshold control module and to provide the clocked comparator with a result of the analog conversion.
7. The amplitude shift keying modulator of claim 1 , wherein a predetermined bias voltage is applied to the rectifier circuit.
8. An amplitude shift keying modulating method comprising:
supplying a bias voltage to a rectifier circuit at a predetermined timing, the rectifier circuit comprising a bias circuit configured to output a direct current voltage, a first MOS transistor in which the direct current voltage is applied between a gate terminal and a source terminal, a second MOS transistor in which the direct current voltage is applied between a gate terminal and a source terminal and a drain terminal thereof is connected to the source terminal of the first MOS transistor, and a coupling capacitor having an end connected to the source terminal of the first MOS transistor and another end from which an alternate current signal is input; and
causing a clocked comparator to operate at a timing different from the predetermined timing, the clocked comparator comparing an input signal rectified by the rectifier circuit with a threshold.