Apparatus for sampling of analog video data from an image pixel array
Disclosed herein is a camera system and camera controller having a modularized design. Camera control functions within the controller are distributed among a number of modules, each module performing a component task of controlling a camera. Individual modules can perform tasks such as generating clock signals, digitizing an analog video signal, and providing multiplexed digital video output. Modules communicate with each other over a common bus sufficient to carry the signals necessary to control the camera. The system implements a RAM-based digital sequencer that provides the capability of loading bit patterns into memory and using these patterns to generate waveforms for clocking a CCD. Clock and readout sequences can be composed in a high level language, compiled and uploaded into the controller. Adjustable clamp and sample signal delays used in digitizing an analog video signal provide the capability to optimize the performance of the system in a given application.
1. An apparatus for sampling of analog video data from an image pixel array comprising:
a sample delay circuit configured to receive a sample signal and sample delay setting data, and further configured to output a delayed sample signal delayed in time by an amount indicated by the sample delay setting data; and
an analog-to-digital converter receiving an analog video input signal from a camera head, said analog-to-digital converter electrically connected to said sample delay circuit, and configured to convert the analog video input signal to a digital video output signal upon receipt of the delayed sample signal,
wherein the sample delay circuit comprises a digital delay line that is configured to delay the sample signal in fixed time increments according to the state of the sample delay setting data to adjust a phase of the delayed sample signal relative to a reset signal, the reset signal being usable to reset pixels of the image pixel array.
2. The apparatus of claim 1 wherein the digital delay line is configured to delay the sample signal in fixed time increments each less than one nanosecond.
3. The apparatus of claim 2 further comprising:
a digital sequencer connected to the adjustable sample delay circuit, the digital sequencer configured to generate the sample signal and reset signal.
4. The apparatus of claim 1 further comprising:
a programmable logic device (PLD) connected to the adjustable sample delay circuit, the PLD configured to generate the sample delay setting data provided to the adjustable sample delay circuit to adjust delay of the delayed sample signal.
5. The apparatus of claim 1 wherein the image pixel array includes a charge-coupled device (CCD).
6. An apparatus for sampling of analog video data from an image pixel array comprising:
a sample delay circuit that is adjustable and that is configured to receive a sample signal and sample delay setting data, and further configured to output a delayed sample signal delayed in time by an amount indicated by the sample delay setting data;
an analog-to-digital converter receiving an analog video input signal from a camera head, said analog-to-digital converter electrically connected to said sample delay circuit, and configured to convert the analog video input signal to a digital video output signal upon receipt of the delayed sample signal; and
a programmable logic device (PLD) connected to the sample delay circuit, the PLD configured to generate the sample delay setting data provided to the sample delay circuit to adjust delay of the delayed sample signal.