IP Library Granted Patent US 7,915,607
Granted Patent B2
US 7,915,607 · App. 12/403,728 · Granted Mar 29, 2011

Nitride semiconductor device

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Quick Facts
Patent No.
US 7,915,607
App. No.
12/403,728
Granted
Mar 29, 2011
Kind
B2
Abstract

A nitride semiconductor device include an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; and an active layer formed between the n-type and p-type nitride semiconductor layers. The active layer has an alternately-layered structure of a plurality of quantum well layers and a plurality of quantum barrier layers, each alternately stacked on each of the quantum well layers. The alternately-layered structure includes a unit multi-layer structure and a thick quantum barrier well. The unit multi-layer structure includes a first quantum well layer, a second quantum well layer formed, a tunneling quantum barrier layer and a crystal quality-improving layer. The thick quantum barrier well may be formed adjacent to the first and second quantum well layers, with a thickness thereof greater than that of the first and second quantum well layers.

Claims (28)

1. A nitride semiconductor device comprising:

an n-type nitride semiconductor layer;

a p-type nitride semiconductor layer; and

an active layer formed between the n-type and p-type nitride semiconductor layers, wherein the active layer has an alternately-layered structure of a plurality of quantum well layers and a plurality of quantum barrier layers, each alternately stacked on each of the quantum well layers,

wherein the alternately-layered structure of a plurality of quantum well layers and a plurality of quantum barrier layers comprises:

a plurality of unit multi-layer structure including a first quantum well layer, a second quantum well layer formed adjacent to the first quantum well layer at a position facing the p-type nitride semiconductor layer, the second quantum well layer having a quantum level higher than that of the first quantum well layer, a tunneling quantum barrier layer disposed between the first and second quantum well layers and a crystal quality-improving layer formed adjacent to the second quantum well layer at a position facing the p-nitride semiconductor layer, the crystal quality-improving layer comprising a quantum barrier layer having a thickness greater than that of the tunneling quantum barrier layer; and

a thick quantum well formed to be between the unit multi-layer structures, adjacent to the first and second quantum well layers, with a thickness thereof being greater than that of the first and second quantum well layers.

2. The nitride semiconductor device of claim 1 , wherein the active layer comprises at least two of the unit multi-layer structures, which are repeatedly stacked on each other.

3. The nitride semiconductor device of claim 2 , wherein the unit multi-layer structures are repeatedly stacked on each other 2 to 30 times.

4. The nitride semiconductor device of claim 2 , wherein the thick quantum well layer is disposed between the unit multi-layer structures, forming an interface with a corresponding one of the tunneling quantum barrier wells of the unit multi-layer structures.

5. The nitride semiconductor device of claim 1 , wherein a part of the alternately-layered structure of a plurality of quantum well layers and a plurality of quantum barrier layers comprises a super-lattice structure.

6. The nitride semiconductor device of claim 5 , wherein the super-lattice structure of the active layer is disposed more adjacent to the n-type nitride semiconductor structure than the unit multi-layer structure is.

7. The nitride semiconductor device of claim 5 , wherein the quantum well layers and the quantum barrier layers included in the super-lattice structure have a thickness ranging from 20 to 60 Å.

8. The nitride semiconductor device of claim 5 , wherein the super-lattice structure includes five to fifteen of the quantum well layers and five to fifteen of the quantum barrier layers.

9. The nitride semiconductor device of claim 5 , wherein the active layer comprises one to five of the unit multi-layer structures.

10. The nitride semiconductor device of claim 5 , wherein the thick quantum well layer is formed between the super-lattice structure and the unit multi-layer structure.

11. The nitride semiconductor device of claim 10 , wherein the thick quantum well layer of the active layer is formed to be more adjacent to the p-type nitride semiconductor layer than to the n-type nitride semiconductor layer.

12. The nitride semiconductor device of claim 10 , wherein the quantum barrier layer formed between the thick quantum barrier well layer and the first quantum well layer of the unit multi-layer structure adjacent to the thick quantum barrier well layer has a thickness ranging from 20 to 60 Å.

13. The nitride semiconductor device of claim 1 , wherein the second quantum well layer has a thickness smaller than the first quantum well layer.

14. The nitride semiconductor device of claim 1 , wherein the first quantum well layer has a thickness ranging from 20 to 60 Å.

15. The nitride semiconductor device of claim 1 , wherein the second quantum well layer has a thickness ranging from 10 to 50 Å.

16. The nitride semiconductor device of claim 1 , wherein the tunneling quantum barrier layer has a thickness ranging from 10 to 80 Å.

17. The nitride semiconductor device of claim 1 , wherein the crystal quality-improving layer has a thickness ranging from 30 to 200 Å.

18. The nitride semiconductor device of claim 1 , wherein the thick quantum well layer has a thickness ranging from 50 to 100 Å.

19. The nitride semiconductor device of claim 1 , wherein the quantum level of the second quantum well layer is realized by doping.

20. The nitride semiconductor device of claim 1 , wherein the unit multi-layer structure further includes:

a third quantum well layer formed adjacent to the first quantum well layer in a position facing the n-type nitride semiconductor layer, the third quantum well layer having a quantum level higher than that of the first quantum well layer; and

a second tunneling quantum well layer formed between the first and third quantum well layers, with a thickness thereof allowing carriers to pass through via tunneling.

Assignments (2)
MERGER Recorded Aug 7, 2012
From: SAMSUNG LED CO., LTD.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 028744/0272 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2010
From: SAMSUNG ELECTRO-MECHANICS CO., LTD.
To: SAMSUNG LED CO., LTD.
Reel/Frame 024723/0532 →