Signal processing apparatus including latch circuit

1. A signal processing apparatus comprising:

a latch circuit comprising a set input terminal, a reset input terminal and an output terminal, and being configured to give a priority to a reset operation;

a set pulse generation circuit configured to generate a set pulse for placing the latch circuit in a set state;

a reset pulse generation circuit connected to the reset input terminal of the latch circuit; and

a correction set signal forming circuit connected to the set pulse generation circuit, the reset pulse generation circuit and the set input terminal of the latch circuit,

wherein the correction set signal forming circuit forms a correction set signal for applying a set instruction continuously during a time period from a time point of a front edge of the set pulse generated from the set pulse generation circuit or a time point delayed from the time point of the front edge to a time point at which the reset pulse is generated, and

wherein the correction set signal forming circuit supplies the correction set signal to the set input terminal of the latch circuit.

2. The signal processing apparatus according to claim 1 , further comprising:

a unit configured to place a load circuit in an off state by an output indicating a set of the latch circuit; and

an abnormality detection circuit which detects an abnormality of the load circuit,

wherein the set pulse generation circuit generates the set pulse in response to an output signal indicating an abnormality from the abnormality detection circuit, and

wherein the reset pulse generation circuit generates the reset pulse in response to that the output signal indicating an abnormality from the abnormality detection circuit disappears.

3. The signal processing apparatus according to claim 1 , wherein the correction set signal forming circuit comprises:

a voltage comparison unit comprising a first input terminal, a second input terminal and an output terminal which is connected to the set input terminal of the latch circuit;

a capacitor which is connected between the first input terminal of the voltage comparison unit and a ground;

a reference voltage source which is connected between the second input terminal of the voltage comparison unit and the ground;

a first constant current circuit which is connected to a DC power supply;

a first reverse current prevention diode which is connected between the first constant current circuit and the capacitor;

a first switch which is connected in parallel to the capacitor via the first reverse current prevention diode;

a second constant current circuit which is connected to the DC power supply;

a second reverse current prevention diode which is connected between the second constant current circuit and the capacitor;

a second switch which is connected in parallel to the capacitor via the second reverse current prevention diode, the second switch having a control terminal connected to the set pulse generation circuit and having characteristics of being placed in an off state in response to the set pulse;

a third constant current circuit which is connected in parallel to the capacitor; and

a switch control circuit which controls the first switch in an off state in response to the output of the comparison unit indicating that the voltage of the capacitor is higher than a reference voltage of the reference voltage source and controls the first switch in an on state in response to the reset pulse.