Method of fabricating an integrated circuit with stress enhancement
A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.
1. A method of fabricating an integrated circuit, the method comprising:
arranging a plurality of cells to form a desired floor plan of the integrated circuit, each cell comprising at least one transistor;
forming a plurality of circuit constituents from the plurality of cells of the floor plan, each circuit constituent comprising at least one cell and belonging to one of a plurality circuit constituent types; and
applying a mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs, including applying the mechanical stress at a first level to cells of circuit constituents belonging to a first portion of the circuit constituent types, and applying the mechanical stress at a second level to cells of circuit constituents belonging to a second portion of the circuit constituent types, wherein the second level is greater than the first level.
2. The method of claim 1 , wherein applying mechanical stress includes:
applying a stress liner at a first thickness over the cells of circuit constituents belonging to the first portion of the circuit constituent types; and
applying a stress liner at a second thickness over the cells of circuit constituents belonging to the second portion of the circuit constituent types, wherein the second thickness is greater than the first thickness.
3. The method of claim 1 , wherein the first portion of circuit constituent types comprises a clock distribution hardware constituent and the second portion of circuit constituent types comprises a remaining portion of circuit constituent types.
4. The method of claim 1 , wherein applying mechanical stress comprises deposition of silicon-germanium in source and drain regions of the transistors of the cells.
5. The method of claim 1 , wherein each circuit constituent type has associated performance variations, and wherein applying mechanical stress includes:
evaluating additional performance variations of each circuit constituent type expected to result from application of mechanical stress to the channel regions of the transistors of the cells thereof and the effect of the additional variations on performance of the integrated circuit; and
applying mechanical stress at the first level to transistors of circuit constituent types having additional expected performance variations that do not adversely affect performance of the integrated circuit, and at the second level to transistors of circuit constituent types having additional expected performance variations adverse to performance of the integrated circuit.
6. The method of claim 1 , wherein performance variations include at least path delay uncertainties associated with the circuit constituent types.
7. The method of claim 1 , wherein the plurality of circuit constituent types includes a very short signal path constituent, and wherein the method includes adding buffers as necessary to short signal path constituents to eliminate hold time variations which would otherwise result from performance enhancements due to application of mechanical stress to channel regions of transistors of the cells of the very short signal path constituents.
8. The method of claim 1 , wherein the circuit constituent types include critical paths.
9. The method of claim 1 , wherein the circuit constituent types include sub-critical paths.
10. The method of claim 1 , wherein the integrated circuit comprises an integrated logic circuit.
11. An integrated circuit comprising:
a plurality of cells arranged to form a desired floor plan, with each cell belonging to one of a plurality of circuit constituent types; and
a stress liner deposited over all cells of the floor plan and having a first thickness over cells belonging to a first portion of the plurality of circuit constituent types and a second thickness over cells belonging to second portion of the plurality of circuit constituent types, wherein the first thickness is greater than the second thickness.
12. The integrated circuit of claim 11 , wherein the second portion of the plurality of circuit constituent types comprises a clock distribution hardware constituent type.
13. The integrated circuit of claim 11 , wherein the integrated circuit comprises an integrated logic circuit.
14. A method of configuring an integrated logic circuit, the method comprising:
arranging a plurality of selected standard cells to form a desired floor plan of the logic circuit, wherein each cell includes a plurality of transistors;
interconnecting the selected standard cells to form a plurality of circuit constituents which together are configured to perform desired functions of the logic circuit, each circuit constituent having associated performance variations, and each circuit constituent belonging to one of a plurality of circuit constituent types;
evaluating additional performance variations for each of the plurality of circuit constituent types which are expected to result from application of mechanical stress to transistors of the corresponding cells; and
applying mechanical stress at varying levels to the channels of transistors of cells of circuit constituent types based on the evaluating.
15. The method of claim 14 , wherein the evaluating includes determining additional delay uncertainties of circuit constituent types expected to result from application of mechanical stress to transistors of the corresponding cells.
16. The method of claim 14 , wherein circuit constituent types include critical paths comprising register cells and combinatorial cells.
17. The method of claim 14 , wherein circuit constituent types include clock distribution hardware constituents.
18. The method of claim 14 , wherein the plurality of circuit constituent types includes a very short signal path constituent, and wherein the method includes adding buffers as necessary to short signal path constituents to eliminate hold time variations which would otherwise result from performance enhancements due to application of mechanical stress to channel regions of transistors of the cells of the very short signal path constituents.
19. A method of fabricating an integrated circuit, the method comprising:
arranging a plurality of cells to form a desired floor plan of the integrated circuit, each cell comprising at least one transistor;
forming a plurality of circuit constituents from the plurality of cells of the floor plan, each circuit constituent comprising at least one cell and belonging to one of a plurality circuit constituent types;
applying a first type of mechanical stress at a first level to cells of circuit constituents belonging to a first portion of the circuit constituent types; and
applying the first type mechanical stress at a second level to cells of circuit constituents belonging to a second portion of the circuit constituent types, wherein the second level is greater than the first level.
20. The method of claim 19 , wherein the first type of mechanical stress comprises a compressive stress.
21. The method of claim 19 , wherein the first type of mechanical stress comprises a tensile stress.