High speed PLL clock multiplier
The present invention relates to a mixed mode electronic circuit that implements a PLL cell that employs an auto-range algorithm to lock to a wide range of input reference signals.
1. A phase locked loop circuit comprising:
an analog portion adapted to generate a voltage controlled oscillator frequency of a voltage controlled oscillator responsive to a wide range of input frequencies; and
a digital portion adapted to selectively over-sample, or not, the voltage controlled oscillator frequency so that the voltage controlled oscillator remains in its linear operating region for a plurality of input frequencies, the digital portion further adapted to wait a number of feedback cycles to allow a loop of the phase locked loop circuit to stabilize.
2. The phase locked loop circuit of claim 1 wherein the digital portion selectively scales a reference clock to automatically maintain the voltage controlled oscillator in its linear operating region.
3. The phase locked loop circuit of claim 2 wherein the analog portion comprises:
a phase frequency detector (PFD) having its input coupled to the digital portion;
a charge pump having its input coupled to an output of the PFD; and
a low pass filter having its input coupled to the output of the charge pump and its output coupled to the voltage controlled oscillator and to a pair of threshold comparators.
4. The phase locked loop circuit of claim 3 wherein the pair of threshold comparators comprises a first comparator that indicates a lower frequency operating state to a finite state machine and a second comparator that represents the higher frequency operating state to the finite state machine.
5. The phase locked loop circuit of claim 4 wherein the first comparator indicates to the finite state machine if VCO control voltage (cntp) is in its linear operating region.
6. The phase locked loop circuit of claim 4 wherein the second comparator indicates to the finite state machine if VCO control voltage (cntp) is in its linear operating region.
7. The phase locked loop circuit of claim 4 wherein the first and second comparators track process parameters of the voltage controlled oscillator to effectively produce a voltage that corresponds to a required range over all a plurality of process corners.
8. A method of operating a PLL circuit, the method comprising:
receiving a clock signal complying with a selected specification; and
operating a finite state machine, in response to outputs of a pair of analog comparators, a digital lock detector, and a watchdog timer, to selectively change a clock divider to maintain a VCO in a stable operating region,
wherein operating the finite state machine includes selectively over-sampling a VCO frequency and waiting a number of feedback cycles to allow a loop of the PLL circuit to stabilize.
9. The method of claim 8 wherein the clock divider is an input clock divider.
10. The method of claim 8 wherein the clock divider is a loop clock divider.
11. The method of claim 8 wherein the watchdog timer determines if the VCO has timely achieved a desired frequency.
12. The method of claim 8 wherein the digital lock detector indicates whether the VCO is locked.
13. The method of claim 12 wherein a the finite state machine restarts an auto-range algorithm if the VCO is not timely locked based on a watchdog, lock detector and comparators status.