Method of IC design optimization via creation of design-specific cells from post-layout patterns
A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power, noise, etc.), which will be then implemented as a standard cell (also known hereafter as metacell), from a set of post-layout patterns. A post-layout pattern represents a part or whole of a standard cell and contains information regarding the pattern including, but not limited to, layout, timing, area, power and noise. As the metacells are created from post-layout patterns, the inaccuracies of prior dynamic library techniques are easily avoided. Such metacells, being design-specific, are optimized to satisfy the constraints imposed by the design context, thus bringing the powerful design-specific customization to standard cell-based design methodology.
1. A method for optimizing an integrated circuit design comprising:
creating a cache of post-layout patterns;
optimizing said integrated circuit design using said cache of post-layout patterns to create design-specific and context-specific standard cells,
wherein said optimizing said integrated circuit design comprises:
a. selecting a connected, multi-input, multi-output sub-set of said standard cells from said integrated circuit design, thereby creating a sub-network;
b. defining constraints to be imposed on the sub-network from said integrated circuit design, and from the sub-network's local context within said integrated circuit design;
c. creating one or more implementations of the sub-network using post-layout patterns from the cache of post-layout patterns;
d. building a design-specific and context-specific standard cell for each implementation determined in the previous step;
e. substituting a newly built design-specific and context-specific standard cell for the sub-network, thereby forming a modified network; and
f. evaluating the characteristics of said modified network with the design-specific and context-specific standard cell, and determining whether to accept or reject the design-specific and context-specific standard cell substitution; and
manufacturing an integrated circuit that uses said design-specific and context-specific standard cells.
2. The method according to claim 1 , wherein the step of selecting uses at least one selection criteria selected from the group consisting of: the physical proximity of standard cells in said integrated circuit design, signal timing, timing criticality, power, area and noise.
3. The method according to claim 1 , wherein said constraints imposed on said sub-network are at least one selected from the group consisting of: signal timing, input capacitance, area, noise and power.
4. The method according to claim 1 , wherein the step of defining derives constraints from cell model characteristics of instances in said integrated circuit design, and from characteristics of said integrated circuit design as a whole, wherein said characteristics are selected from the group consisting of: signal timing, drive strength, physical location, area, power, noise and combinations thereof.
5. The method according to claim 1 , wherein the step of defining derives constraints from standard cell model characteristics selected from the group consisting of: permissible number of fan outs, permissible transition times, delay, power, area, noise, and combinations thereof.
6. The method according to claim 1 , wherein the step of creating comprising:
a. creating one or more sets of post-layout patterns, where said patterns are taken from said post-layout cache, and where said patterns in each of said sets can be interconnected to produce the same function as the sub-network; and
b. selecting one or more of said sets of post-layout patterns that satisfy some, or all, of said constraints placed on the sub-network.
7. The method according to claim 6 , wherein the step of selecting uses at least one process selected from the group consisting of: placing the set of post-layout patterns, routing the interconnections between the post-layout patterns, polygon merging, polygon fracturing, extracting the circuit, extracting layout parasitics and simulating the interconnected post-layout patterns.
8. The method according to claim 6 , wherein the step of selecting is based on at least one characteristic of said set of interconnected post-layout patterns selected from the group consisting of: signal timing, input capacitance, area, power and noise.
9. The method according to claim 8 , wherein said characteristics are either estimated or evaluated accurately.
10. The method according to claim 1 , wherein the step of building produces some or all of the representations required of a standard cell in the standard cell library, wherein said representations are at least one selected from the group consisting of: net list, signal timing, input capacitance, power, noise, area, layout geometry, and layout parasitics.
11. The method of claim 10 , wherein said representations are as accurate as those in said standard cell library.
12. The method according to claim 1 , wherein the step of evaluating uses at least one characteristic of the design selected from the group consisting of: signal timing, power, area and noise.