IP Library Granted Patent US 7,941,794
Granted Patent B2
US 7,941,794 · App. 11/212,598 · Granted May 10, 2011

Data flow graph processing method and processing apparatus provided with reconfigurable circuit

Assignee: Sanyo Electric Co., Ltd.
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Quick Facts
Patent No.
US 7,941,794
App. No.
11/212,598
Granted
May 10, 2011
Kind
B2
Abstract

A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order of execution of DFGs corresponding to respective subprograms. DFGs are converted into configuration data and the flow data is converted into control data.

Claims (6)

1. An apparatus having data flow graph (DFG) processor, which processes a DFG necessary for configuration of a reconfigurable circuit capable of changing functions, comprising:

a central processing unit;

a dividing unit which divides a program describing target operations into two or more subprograms;

a DFG generating unit which generates, using the central processing unit, a plurality of DFGs corresponding to the two or more subprograms in accordance with a description in the program, the DFGs representing dependency in execution between the target operations of the program carried out in sequence, wherein the generating unit generates, when a branching process is detected in the program, a first DFG of the plurality of DFGs indicating a process before the branching process, and a second DFG of the plurality of DFGs indicating a process after the branching process, and at least either one of the first DFG or the second DFG includes a process for determining a destination of the branching process;

a flow data generating unit which generates flow data indicating the order of execution of the DFGs based on the generation by the DFG generating unit; and

a configuration data generating unit which converts the DFGs into corresponding configuration data for mapping the DFGs into the reconfigurable circuit and defining the functions in the reconfigurable circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2014
From: SANYO ELECTRIC CO., LTD.
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 032077/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2005
From: OZONE, MAKOTO; NAKAJIMA, HIROSHI; HIRAMATSU, TATSUO; HIRASE, KATSUNORI; OKADA, MAKOTO
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 016935/0052 →
Priority Claims (3)
JP 2004-250666 · Aug 30, 2004 · national
JP 2004-250671 · Aug 30, 2004 · national
JP 2005-081919 · Mar 22, 2005 · national
Continuity (1)
Related Publication 20060048113A1 · Mar 2, 2006