Method of manufacturing an array substrate for LCD device having double-layered metal structure
An array substrate in a liquid crystal display device includes a gate electrode, a gate line and a gate pad on a substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure consisting of a first metal layer and a first barrier metal layer in series from the substrate, and wherein the first metal is one of aluminum and aluminum alloy; a gate insulation laver; an active layer and an ohmic contact layer; a data line, source and drain electrodes, and a data pad each having a double-layered structure consisting of a second barrier metal layer and a second metal layer of copper; a passivation layer; and a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer formed of a transparent conductive material.
1. A method of forming an array substrate for use in a liquid crystal display device, comprising:
forming a first metal layer and a first barrier metal layer in series on a substrate, wherein the first metal layer is one of aluminum and aluminum alloy;
patterning simultaneously both the first metal layer and the first barrier metal layer using a first mask process to form a gate electrode, a gate line and a gate pad on the substrate, wherein the gate electrode, the gate line and the gate pad have a double-layered structure consisting of the metal layer and the first barrier metal layer;
forming a gate insulation layer on the substrate to cover the double-layered gate electrode, line and pad;
forming an active layer and an ohmic contact layer sequentially on the gate insulation layer using a second mask process;
forming sequentially a second barrier metal layer and a second metal layer of copper on the gate insulation layer to cover the active layer and the ohmic contact layer;
patterning simultaneously both the second barrier metal layer and the second metal layer of copper using a third mask process to form a data line, source and drain electrodes and a data pad, wherein the data line is on the gate insulation layer and crossed the gate line, and wherein the data line, the source and drain electrodes, the capacitor electrode and the data pad have a double-layered structure including the second barrier metal layer and the second metal layer of copper;
forming a passivation layer formed on the gate insulation layer to cover the double-layered data line, source and drain electrodes, and data pad;
patterning the second passivation layer using a fourth mask process to form a drain contact hole exposing the drain electrode, a gate pad contact hole exposing the gate pad, and a data pad contact hole exposing the data pad; and
forming a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer using a fifth mask process.
2. The method according to claim 1 , wherein each of the first and second barrier metal layer is formed of a metallic material selected from a group consisting of tantalum (Ta) titanium (Ti), molybdenum (Mo), molybdenum alloy (Mo-alloy), chromium (Cr), tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), nickel (Ni), indium (In), tin (Sn), gold (Au), and an alloy thereof.
3. The method according to claim 1 , wherein each of the first and second barrier metal layers has a thickness of 100 to 1000 angstroms.
4. The method according to claim 1 , wherein the second metal layer of copper has a thickness of 1000 to 2000 angstroms.
5. The method according to claim 1 , wherein the gate electrode extends from the gate line, and the gate pad is at an end of the gate line.
6. The method according to claim 1 , wherein the source and drain electrodes contact the ohmic contact layer, and the data pad is disposed on the gate insulation layer.
7. The method according to claim 1 , wherein the source electrode extends from the data line, the drain electrode is spaced apart from the source electrode, and the data pad is at an end of the data line.
8. The method according to claim 1 , wherein the pixel electrode is disposed in a pixel region defined by a crossing of the gate and data lines, and wherein said pixel electrode contacts the drain electrode through the drain contact hole, the gate pad terminal contacts the gate pad through the gate pad contact hole, and the data pad terminal contacts the data pad through the data pad contact hole.
9. The method according to claim 1 , wherein forming the data line, the source and drain electrodes and the data pad includes forming a double-layered capacitor electrode on the gate insulation layer.
10. The method according to claim 9 , wherein the double-layered capacitor electrode overlaps a portion of the gate line, includes of the second barrier metal layer and the second metal layer of copper, and is connected in parallel with the pixel electrode through a contact hole formed in the passivation layer.