Synchronous read channel
View Patent ↗A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
1. An integrated circuit synchronous read channel for receiving digitized read signals representing digitized samples of a read signal of a magnetic storage device and recovering digital data represented thereby, the integrated circuit comprising:
at least one detector, responsive to the digitized read signals, that operates to:
detect characteristics of the digitized read signals indicative of storage media transitions; and
receive a stream of the digitized read signals and determine a corresponding sequence of binary digital signals likely to be represented by the received stream of the digitized read signals;
a timing recovery circuit, responsive to the digitized read signals and an output of the at least one detector, that operates to provide a timing control signal for controlling the timing of digitized samples of the read signal; and
an RLL (d,k) decoder that operates to provide a run length limited decoded output by decoding the sequence of binary digital signals determined by the at least one detector.
2. The integrated circuit synchronous read channel of claim 1 further comprising a digital pulse shaping filter that operates to modify the digitized read signals prior to receipt thereof by at least one of (i) the at least one detector and (ii) the timing recovery circuit.
3. The integrated circuit synchronous read channel of claim 2 wherein the digital pulse shaping filter comprises variable filter parameters.
4. The integrated circuit synchronous read channel of claim 2 wherein the digital pulse shaping filter comprises programmable filter parameters.
5. The integrated circuit synchronous read channel of claim 2 further comprising a spectrum smoothing filter that operates to filter the digitized read signals prior to processing by the at least one detector.
6. The integrated circuit synchronous read channel of claim 1 , wherein the at least one detector allows selection between center and side sampling of the digitized read signals.
7. The integrated circuit synchronous read channel of claim 1 , wherein the at least one detector accommodates pulse asymmetry in the digitized read signals.
8. The integrated circuit synchronous read channel of claim 1 , wherein the at least one detector comprises a partial response sequence detector.
9. The integrated circuit synchronous read channel of claim 1 , wherein the timing recovery circuit operates in a plurality of different modes comprising an acquisition mode and a tracking mode.
10. The integrated circuit synchronous read channel of claim 1 , wherein the timing recovery circuit is programmable.
11. The integrated circuit synchronous read channel of claim 1 , wherein the timing recovery circuit operates to compute at least one of phase error and frequency error.
12. The integrated circuit synchronous read channel of claim 1 , wherein the timing recovery circuit operates to compute timing error at transition times.
13. The integrated circuit synchronous read channel of claim 1 , wherein the RLL (d, k) decoder operates to provide a run length limited decoded output by decoding a sequence of binary digital signals from the at least one detector.
14. The integrated circuit synchronous read channel of claim 1 , wherein the digitized read signals comprise a plurality of parallel digital signals.
15. The integrated circuit synchronous read channel of claim 1 , wherein the type of data output from the RLL (d, k) decoder is user-selectable.
16. The integrated circuit synchronous read channel of claim 1 , wherein the timing recovery circuit operates to feed back the timing control signal to circuitry that samples the read signal of the magnetic storage device.
17. The integrated circuit synchronous read channel of claim 9 , wherein the acquisition mode corresponds to a first frequency control range and a first frequency control resolution, and the tracking mode corresponds to a second frequency control range different from the first frequency control range and a second frequency control resolution different from the first frequency control resolution.
18. The integrated circuit synchronous read channel of claim 1 , wherein the at least one detector comprises a Viterbi detector.
19. The integrated circuit synchronous read channel of claim 1 , wherein d=1.
20. The integrated circuit synchronous read channel of claim 1 , wherein the at least one detector comprises a digital peak detector and a sequence detector.
21. A disk drive comprising:
a magnetic storage device; and
an integrated circuit synchronous read channel for receiving digitized read signals representing digitized samples of a read signal of the magnetic storage device and recovering digital data represented thereby, the integrated circuit comprising:
at least one detector, responsive to the digitized read signals, that operates to:
detect characteristics of the digitized read signals indicative of storage media transitions; and
receive a stream of the digitized read signals and determine a corresponding sequence of binary digital signals likely to be represented by the received stream of the digitized read signals;
a timing recovery circuit, responsive to the digitized read signals and an output of the at least one detector, that operates to provide a timing control signal for controlling the timing of digitized samples of the read signal; and
an RLL (d,k) decoder that operates to provide a run length limited decoded output by decoding the sequence of binary digital signals determined by the at least one detector.
22. An integrated circuit synchronous read channel for receiving digitized read signals representing digitized samples of a read signal of a magnetic storage device and recovering digital data represented thereby, the integrated circuit comprising:
a timing recovery circuit, responsive to the digitized read signals, that operates to provide a timing control signal for controlling the timing of digitized samples of the read signal;
a sequence detector, responsive to the digitized read signals, that operates to receive a stream of the digitized read signals and determine a corresponding sequence of binary digital signals likely to be represented by the received stream of the digitized read signals; and
an RLL (d,k) decoder that operates to provide a run length limited decoded output by decoding the sequence of binary digital signals determined by the sequence detector.