IP Library Granted Patent US 7,964,862
Granted Patent B2
US 7,964,862 · App. 12/056,227 · Granted Jun 21, 2011

Phase change memory devices and methods for manufacturing the same

Assignee: Industrial Technology Research Institute
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Quick Facts
Patent No.
US 7,964,862
App. No.
12/056,227
Granted
Jun 21, 2011
Kind
B2
Abstract

Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a first electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer and the first electrode. A phase change material layer disposed in the second dielectric layer to electrically contact the first electrode. A third dielectric layer is disposed over the second dielectric layer. A second electrode is disposed in the third dielectric layer to electrically connect the phase change material layer and at least one gap disposed in the first dielectric layer or the second dielectric layer to thereby isolate portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto.

Claims (35)

1. A phase change memory device, comprising:

a first electrode disposed in a first dielectric layer;

a second dielectric layer disposed over the first dielectric layer and the first electrode;

a phase change material layer disposed in the second dielectric layer, electrically contacting the first electrode;

a third dielectric layer disposed over the second dielectric layer;

a second electrode disposed in the third dielectric layer, electrically contacting the phase change material layer; and

at least one gap disposed in the first dielectric layer or the second dielectric layer, thereby isolating portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto.

2. The phase change memory device as claimed in claim 1 , wherein the at least one gap is disposed in the second dielectric layer to isolate portions of a sidewall of the phase change material layer and the second dielectric layer.

3. The phase change memory device as claimed in claim 2 , further comprising a spacer layer disposed between the sidewall of the phase change material layer and the at least one gap.

4. The phase change memory device as claimed in claim 1 , wherein the at least one gap is disposed in the first dielectric layer to isolate portions of a bottom surface of the phase change material layer and the first dielectric layer.

5. The phase change memory device as claimed in claim 4 , wherein the at least one gap is disposed on a sidewall of the first electrode to isolate the first electrode and the first dielectric layer.

6. A phase change memory device, comprising:

a first electrode disposed in a first dielectric layer;

a second dielectric layer disposed over the first dielectric layer and the first electrode;

an I-shaped phase change material layer disposed in the second dielectric layer, electrically contacting the first electrode, comprising;

a first portion contacting the first electrode, having a first width;

a second portion disposed on a portion of the first portion, having a second width;

a third portion disposed on the second portion and partially contacting the second portion, having a third width, wherein the second width is less than the first width and the third width;

a third dielectric layer disposed over the second dielectric layer and the I-shaped phase change material layer;

a second electrode disposed in the third dielectric layer, electrically contacting the third portion of the phase change material layer;

a spacer layer at least disposed between portions of the second portion of the I-shaped phase change material layer and the second dielectric layer; and

at least one gap disposed between the spacer layer and the second dielectric layer.

7. The phase change memory device as claimed in claim 6 , wherein the second portion of the I-shaped phase change material layer has an L or reverse L ( ) shaped cross section.

8. The phase change memory device as claimed in claim 6 , further comprising a dielectric plug embedded in the second portion of the I-shaped phase change material layer, wherein the dielectric plug is merely in contact with the first and third portions of the I-shaped phase change material layer but not in contact with the spacer layer.

9. The phase change memory device as claimed in claim 8 , wherein the second portion of the I-shaped phase change material layer surrounds sidewalls of the dielectric plug.

10. The phase change memory device as claimed in claim 6 , wherein the I-shaped phase change material layer comprises chalcogenide materials.

11. The phase change memory device as claimed in claim 6 , wherein the first and second electrodes comprise Ti, Al, Cu, W or alloys thereof.

12. A phase change memory device, comprising:

a first electrode disposed in a first dielectric layer;

a second dielectric layer disposed over the first dielectric layer and the first electrode;

a phase change material layer disposed in the second dielectric layer, electrically contacting the first electrode;

a third dielectric layer disposed over the phase change material layer and the second dielectric layer;

a second electrode disposed in the third dielectric layer, electrically contacting the phase change material layer; and

at least one gap disposed in the first dielectric layer, thereby isolating portions of a bottom surface of the phase change material layer with the first dielectric layer.

13. The phase change memory device as claimed in claim 12 , wherein the at least one gap surrounds a sidewall of the first electrode to isolate the first electrode with the first dielectric layer adjacent to the first electrode.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2026
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: HIGGS OPL. CAPITAL LLC
Reel/Frame 075733/0186 →
MERGER Recorded Dec 26, 2015
From: HIGGS OPL. CAPITAL LLC
To: GULA CONSULTING LIMITED LIABILITY COMPANY
Reel/Frame 037360/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2011
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
To: HIGGS OPL. CAPITAL LLC
Reel/Frame 027364/0397 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2010
From: POWERCHIP SEMICONDUCTOR CORP.; NANYA TECHNOLOGY CORPORATION; PROMOS TECHNOLOGIES INC.; WINBOND ELECTRONICS CORP.
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 024149/0102 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2008
From: CHEN, FREDERICK T; CHUO, YEN; HSU, HONG-HUI; YEH, JYI-TYAN; TSAI, MING-JINN
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE; POWERCHIP SEMICONDUCTOR CORP.; NANYA TECHNOLOGY CORPORATION; PROMOS TECHNOLOGIES INC.; WINBOND ELECTORNICS CORP.
Reel/Frame 020728/0334 →
Priority Claims (1)
TW 96114371 A · Apr 24, 2007 · national
Continuity (1)
Related Publication 20080265238A1 · Oct 30, 2008