Loading the input memory of an LDPC decoder with data for decoding

1. A process comprising:

loading an input memory of an LDPC decoder with data corresponding to an LDPC frame to be decoded and comprising a number N of log-likelihood ratios, or LLRs, of which a number K are information LLRs and a number N−K are parity LLRs, where N and K are integers, wherein:

at least one stream is formed of binary words of a first type, each corresponding to multiple information LLRs, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out (FIFO) ring buffer, and

first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and second memory accesses are made in page mode in order to write the binary words of the second type to a second zone of the input memory.

2. The process according to claim 1 wherein, as the second zone of the input memory comprises a specific number Wb of rows, the FIFO has a capacity of Wb binary words.

3. The process according to claim 1 wherein, as the first zone of the input memory is addressable by binary words each corresponding to a number L of parallel LLRs where L is a specific integer, the serial/parallel converter outputs the binary words of the first type as binary words corresponding to a number L of parallel information LLRs.

4. The process according to claim 1 wherein, as the second zone of the input memory is addressable by binary words each corresponding to a number L of parallel LLRs where L is a specific integer, the binary words of the second type are binary words corresponding to a number L of parallel parity LLRs, and the binary words stored in the FIFO are binary words corresponding to a number L−1 of parallel parity LLRs, with each such word issued by the FIFO supplemented by a parity LLR to form a binary word of the second type.

5. The process according to claim 1 wherein, as the LLRs are received in the form of a stream of interlaced LLRs with an interlacing depth corresponding to a number Q of LLRs, a deinterlacing is performed by forming in parallel a number Q 1 of streams of binary words of the first type by means of Q 1 respective serial/parallel conversion modules, and a number Q 2 of streams of binary words of the second type by means of Q 2 respective row/column interlacing devices each comprising a two-dimensional FIFO ring buffer, where Q 1 and Q 2 are specific integers which depend on a code rate

K

N

of an LDPC coding and are such that Q 1 +Q 2 ≧Q.

6. The process according to claim 5 wherein:

the number Q 1 of streams of binary words of the first type is equal to

Q

×

K

N

if the number

Q

×

K

N

is an integer, else is equal to

floor

⁡

(

Q

×

K

N

)

+

1

,

and

the number Q 2 of streams of binary words of the second type is equal to

Q

×

(

1

-

K

N

)

if the number

Q

×

K

N

is an integer, else is equal to

Q

-

floor

(

Q

×

K

N

)

,

where “floor” indicates a mathematical function which returns the greatest integer less than a number passed as an argument.

7. The process according to claim 5 wherein the number which is equal to

N

Q

×

L

is an integer.

8. The process according to claim 5 wherein the number which is equal to

N

Q

(

N

-

K

)

×

L

P

is an integer, where P indicates a parallelism index for the LDPC decoder.

9. A device for loading an input memory of an LDPC decoder with data corresponding to an LDPC frame to be decoded and comprising a number N of log-likelihood ratios, or LLRs, of which a number K are information LLRs and a number N−K are parity LLRs, where N and K are integers, comprising:

at least one serial/parallel conversion module configured to form a stream of binary words of a first type, each corresponding to multiple information LLRs;

at least one row/column interlacing device which comprises a two-dimensional first-in first-out (FIFO) ring buffer and which is configured to form a stream of binary words of a second type, each corresponding to multiple parity LLRs; and a memory access control unit configured to write in page mode the binary words of the first type into a first zone of the input memory, and to write the binary words of the second type into a second zone of the input memory.

10. The device according to claim 9 wherein, as the second zone of the input memory comprises a given number Wb of rows, the FIFO has a capacity of Wb binary words.

11. The device according to claim 9 wherein, as the first zone of the input memory is addressable by binary words each corresponding to a number L of parallel LLRs where L is a specific integer, the serial/parallel converter is able to output the binary words of the first type as binary words corresponding to a number L of parallel information LLRs.

12. The device according to claim 9 wherein, as the second zone of the input memory is addressable by binary words each corresponding to a number L of parallel LLRs where L is a specific integer, the binary words of the second type are binary words corresponding to a number L of parallel parity LLRs, and the binary words stored in the FIFO are binary words corresponding to a number L−1 of parallel parity LLRs, with the device able to supplement each word issued by the FIFO with a parity LLR to form a binary word of the second type.

13. The device according to claim 9 wherein, as the LLRs are received in a form of a stream of interlaced LLRs with a depth of interlacing corresponding to a number Q of LLRs, the device is able to deinterlace the LLRs and comprises for this purpose a number Q 1 of serial/parallel conversion modules to form in parallel Q 1 respective streams of binary words of the first type, and a number Q 2 of row/column interlacing devices to form Q 2 respective streams of binary words of the second type, with said Q 2 row/column interlacing devices each comprising a two-dimensional FIFO ring buffer, where Q 1 and Q 2 are specific integers which depend on the code rate

K

N

of the LDPC coding and are such that Q 1 +Q 2 ≧Q.

14. The device according to claim 13 wherein:

the number Q 1 of streams of binary words of the first type is equal to

Q

×

K

N

if the number

Q

×

K

N

is an integer, else is equal to

floor

⁢

⁢

(

Q

×

K

N

)

+

1

,

and

the number Q 2 of streams of binary words of the second type is equal to

Q

×

(

1

-

K

N

)

if the number

Q

×

K

N

is an integer, else is equal to

Q

-

floor

(

Q

×

K

N

)

,

where “floor” indicates a mathematical function which returns the greatest integer less than a number passed as an argument.

15. The device according to claim 13 wherein the number which is equal to

N

Q

×

L

is an integer.

16. The device according to claim 13 wherein the number which is equal to

N

Q

(

N

-

K

)

×

L

P

is an integer, where P indicates a parallelism index for the LDPC decoder.

17. An LDPC decoder comprising:

an input memory with data corresponding to an LDPC frame to be decoded and comprising a number N of log-likelihood ratios, or LLRs, of which a number K are information LLRs and a number N−K are parity LLRs, where N and K are integers;

at least one serial/parallel conversion module configured to form a stream of binary words of a first type, each corresponding to multiple information LLRs, as well as at least one row/column interlacing device which comprises a two-dimensional first-in first-out ring buffer and which is configured to form a stream of binary words of a second type, each corresponding to multiple parity LLRs; and

a memory access control unit configured to write in page mode the binary words of the first type into a first zone of the input memory, and to write the binary words of the second type into a second zone of the input memory.

18. The LDPC decoder of claim 17 wherein, as the second zone of the input memory comprises a given number Wb of rows, the FIFO has a capacity of Wb binary words.

19. The LDPC decoder of claim 17 wherein, as the first zone of the input memory is addressable by binary words each corresponding to a number L of parallel LLRs where L is a specific whole number, the serial/parallel converter is able to output the binary words of the first type as binary words corresponding to a number L of parallel information LLRs.

20. The LDPC decoder of claim 17 wherein as the LLRs are received in a form of a stream of interlaced LLRs with a depth of interlacing corresponding to a number Q of LLRs, the device is able to deinterlace the LLRs and comprises for this purpose a number Q 1 of serial/parallel conversion modules to form in parallel Q 1 respective streams of binary words of the first type, and a number Q 2 of row/column interlacing devices to form Q 2 respective streams of binary words of the second type, with said Q 2 row/column interlacing devices each comprising a two-dimensional FIFO ring buffer, where Q 1 and Q 2 are specific whole numbers which depend on the code rate

K

N

of the LDPC coding and are such that Q 1 +Q 2 ≧Q.

21. The LDPC decoder of claim 20 wherein the number which is equal to

N

Q

×

L

is a whole number.

22. The LDCP decoder of claim 20 wherein the number which is equal to

N

Q

(

N

-

K

)

×

L

P

is a whole number, where P indicates a parallelism index for the LDPC decoder.

23. An apparatus comprising:

an LDPC decoder including an input memory with data corresponding to an LDPC frame to be decoded and comprising a number N of log-likelihood ratios, or LLRs, of which a number K are information LLRs and a number N−K are parity LLRs, where N and K are whole numbers;

at least one serial/parallel conversion module configured to form a stream of binary words of a first type, each corresponding to multiple information LLRs;

at least one row/column interlacing device which comprises a two-dimensional first-in first-out ring buffer and which is configured to form a stream of binary words of a second type, each corresponding to multiple parity LLRs; and

a memory access control unit configured to write in page mode the binary words of the first type into a first zone of the input memory, and to write the binary words of the second type into a second zone of the input memory.

24. The apparatus of claim 23 wherein, as the second zone of the input memory comprises a given number Wb of rows, the FIFO has a capacity of Wb binary words.

25. The apparatus of claim 23 wherein, as the first zone of the input memory is addressable by binary words each corresponding to a number L of parallel LLRs where L is a specific whole number, the serial/parallel converter is able to output the binary words of the first type as binary words corresponding to a number L of parallel information LLRs.

26. The apparatus of claim 23 wherein as the LLRs are received in a form of a stream of interlaced LLRs with a depth of interlacing corresponding to a number Q of LLRs, the device is able to deinterlace the LLRs and comprises for this purpose a number Q 1 of serial/parallel conversion modules to form in parallel Q 1 respective streams of binary words of the first type, and a number Q 2 of row/column interlacing devices to form Q 2 respective streams of binary words of the second type, with said Q 2 row/column interlacing devices each comprising a two-dimensional FIFO ring buffer, where Q 1 and Q 2 are specific whole numbers which depend on the code rate

K

N

of the LDPC coding and are such that Q 1 +Q 2 ≧Q.

27. The apparatus of claim 26 wherein the number which is equal to

N

Q

×

L

is a whole number.

28. The apparatus of claim 26 wherein the number which is equal to

N

Q

(

N

-

K

)

×

L

P

is a whole number, where P indicates a parallelism index for the LDPC decoder.

29. The apparatus of claim 26 , further comprising a demodulator.