Sigma-delta modulator including truncation and applications thereof
A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments, the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.
1. A sigma-delta modulator circuit comprising:
a first combiner configured to combine an input signal and a first feedback signal;
a first integrator configured to integrate an output of the first combiner and to produce a first multi-bit output;
a first truncator configured to receive the first multi-bit output and to truncate a least significant bit from the first multi-bit output; and
a first modulation stage configured to combine the output of the first truncator and a second feedback signal, and further configured to produce a second multi-bit output.
2. The sigma-delta modulator circuit of claim 1 , wherein the first combiner is configured to sample the input signal, wherein the input signal is at a frequency of at least 4 GHz.
3. The sigma-delta modulator circuit of claim 1 , wherein the first truncator is configured to truncate two bits from the first multi-bit output.
4. The sigma-delta modulator circuit of claim 1 , wherein the first truncator comprises a second order truncation circuit.
5. The sigma-delta modulator circuit of claim 1 , wherein the first truncator includes a feedback loop configured to generate a feedback using the least significant bit.
6. The sigma-delta modulator circuit of claim 1 , wherein the first feedback signal is different from the second feedback signal.
7. The sigma-delta modulator circuit of claim 1 , wherein the first feedback signal is alternatively combined with different bits of the input signal.
8. The sigma-delta modulator circuit of claim 1 , wherein the first combiner and the first truncator include adders having only two signal inputs each.
9. The sigma-delta modulator circuit of claim 1 , wherein the first modulation stage includes a second combiner configured to combine the output of the first truncator and the second feedback signal, and further includes a second integrator configured to integrate an output of the second combiner and to produce the second multi-bit output.
10. The sigma-delta modulator circuit of claim 9 , further comprising a second truncator configured to receive the second multi-bit output and to truncate a least significant bit from the second multi-bit output.
11. The sigma-delta modulator circuit of claim 10 , wherein the second truncator is configured to truncate more than two bits from the second multi-bit output.
12. The sigma-delta modulator circuit of claim 10 , further comprising a second modulation stage including a third combiner and a third integrator, the third combiner configured to combine the output of the second truncator and a third feedback signal, the third integrator being configured to integrate an output of the third combiner to produce a third multi-bit output.
13. The sigma-delta modulator circuit of claim 12 , further comprising a quantizer configured to quantize the third multi-bit output.
14. The sigma-delta modulator circuit of claim 13 , further comprising a feedback generator configured to generate the first, second, and third feedback signals from an output of the quantizer.
15. The sigma-delta modulator circuit of claim 14 , wherein the feedback generator is configured to result in a gain of approximately 1.6 in a feedback loop including the first modulation stage, the quantizer, and the feedback generator.
16. The sigma-delta modulator circuit of claim 14 , wherein the feedback generator is configured to produce a gain between one and two in a feedback loop including the first modulation stage.
17. A method comprising:
combining a signal with a first feedback signal to produce a first combined signal;
integrating the first combined signal to produce a first multi-bit output;
truncating a least significant bit from the first multi-bit output;
combining the truncated first multi-bit output with a second feedback signal to produce a second combined signal;
integrating the second combined signal to produce a second multi-bit output;
deriving the first feedback signal and the second feedback signal from the second multi-bit output.
18. The method of claim 17 , wherein deriving the first and second feedback signals from the second multi-bit output includes truncating the second multi-bit output, combining the truncated second multi-bit output with a third feedback signal to produce a third combined signal, and integrating the third combined signal to produce a third multi-bit output.
19. The method of claim 18 , wherein deriving the first and second feedback signals from the second multi-bit output further includes quantizing the third multi-bit output.
20. The method of claim 17 , wherein combining the signal with the first feedback signal to produce the first combined signal includes sampling the input signal.
21. The method of claim 17 , wherein truncating the first multi-bit output includes truncating two bits from the first multi-bit output.