Low voltage non-volatile memory with charge trapping layer
View Patent ↗Methods, circuits, processes, devices, and/or arrangements for a non-volatile memory (NVM) cell operable at relatively low voltages are disclosed. In one embodiment, an NVM cell can include: (i) a gate over a charge trapping layer, the charge trapping layer being insulated from the gate by a first insulating layer, the charge trapping layer being insulated from a channel by a second insulating layer; and (ii) source and drain on either side of the channel, the channel being under the second insulating layer, where the NVM cell is configured to be erased by channel-induced hot holes (CHH).
1. A non-volatile memory (NVM) cell, comprising:
a) a gate over a charge trapping layer, said charge trapping layer being insulated from said gate by a first insulating layer, said charge trapping layer being insulated from a channel by a second insulating layer; and
b) source and drain on either side of said channel, said channel being under said second insulating layer, wherein said NVM cell is configured to be erased by channel-induced hot holes (CHH) that are produced by ramping down a voltage on said gate from a first positive voltage level to a second positive voltage level,
c) wherein said NVM cell is configured to be programmed through said second insulating layer when in a high throughput mode by Fowler-Nordheim (F-N) tunneling, and when in a field programming mode by channel hot electron (CHE) injection.
2. The NVM cell of claim 1 , wherein said charge trapping layer is configured to be programmed using said F-N tunneling through said second insulating layer when in said high throughput mode.
3. The NVM cell of claim 1 , wherein said charge trapping layer is configured to be programmed using said CHE injection through said second insulating layer when in said field programming mode.
4. The NVM cell of claim 1 , wherein said first positive voltage level is about 4V, and said second positive voltage level is about 1 V.
5. The NVM cell of claim 1 , wherein said first and second insulating layers and said charge trapping layer each comprise a first material.
6. The NVM cell of claim 5 , wherein said first material comprises a high-k material.
7. The NVM cell of claim 1 , wherein said first and second insulating layers comprise oxide, and said charge trapping layer comprises a high-k material.
8. The NVM cell of claim 1 , wherein said first insulating layer comprises oxide, and said second insulating layer comprises a high-k material.
9. The NVM cell of claim 1 , wherein said first insulating layer comprises a high-k material, and said second insulating layer comprises oxide.
10. The NVM cell of claim 1 , wherein said first and second insulating layers comprise oxide.
11. The NVM cell of claim 1 , wherein said first and second insulating layers comprise high-k material.
12. The NVM cell of claim 1 , wherein said charge trapping layer comprises nanocrystals.
13. The NVM cell of claim 1 , wherein the charge trapping layer comprises nitride or oxynitride.
14. The NVM cell of claim 1 , wherein said gate comprises polysilicon.
15. The NVM cell of claim 1 , wherein said gate comprises metal.
16. A non-volatile memory (NVM) cell circuit, comprising:
a) a gate over a charge trapping layer, said charge trapping layer being insulated from said gate by a first insulating layer, said charge trapping layer being insulated from a channel by a second insulating layer;
b) source and drain on either side of said channel, said channel being under said second insulating layer;
c) a program control circuit configured to apply a first voltage on said gate, a second voltage on said source, and a third voltage on said drain, wherein said first, second, and third voltages are sufficient to induce Fowler-Nordheim (F-N) tunneling through said second insulating layer when in a high throughput mode, and to induce channel hot electron (CHE) injection through said second insulating layer when in a field programming mode; and
d) an erase control circuit configured to apply a fourth voltage on said gate, a fifth voltage on said source, and a sixth voltage on said drain, said fourth, fifth, and sixth voltages being sufficient for channel-induced hot holes (CHH) through said second insulating layer, said CHH being produced by ramping down said fourth voltage from a first positive voltage level to a second positive voltage level.
17. The NVM cell circuit of claim 16 , wherein said charge trapping layer comprises nitride or oxynitride.
18. The NVM cell circuit of claim 16 , wherein said first and second insulating layers each comprise oxide.
19. The NVM cell circuit of claim 16 , wherein said first, second, and third voltages are sufficient to induce said F-N tunneling through said second insulating layer to program said charge trapping layer when in said high throughput mode.
20. The NVM cell circuit of claim 16 , wherein said first, second, and third voltages are sufficient to induce said CHE injection through said second insulating layer to program said charge trapping layer when in said field programming mode.
21. The NVM cell circuit of claim 20 , wherein said first voltage is about 5.5 V.
22. The NVM cell circuit of claim 20 , wherein said second and said fifth voltages are each about 0 V.
23. The NVM cell circuit of claim 20 , wherein said third and said sixth voltages are each about 5 V.
24. The NVM cell circuit of claim 16 , wherein said high throughput mode is used to program a plurality of NVM cells in one-shot.
25. The NVM cell circuit of claim 16 , wherein said first positive voltage level is about 4V, and said second positive voltage level is about 1 V.
26. An electrically erasable programmable read-only memory (EEPROM) device, comprising:
a) a controller configured to control programming, erasing, and reading of a memory portion; and
b) said memory portion comprising a non-volatile memory (NVM) cell having: (i) a gate over a charge trapping layer, said charge trapping layer being insulated from said gate by a first insulating layer, said charge trapping layer being insulated from a channel by a second insulating layer; and (ii) source and drain on either side of said channel, said channel being under said second insulating layer, wherein said charge trapping layer of said NVM cell is configured to be erased by channel-induced hot holes (CHH) that are produced by ramping down a voltage on said gate from a first positive voltage level to a second positive voltage level, wherein said NVM cell is configured to be programmed through said second insulating layer when in a high throughput mode by Fowler-Nordheim (F-N) tunneling, and when in a field programming mode by channel hot electron (CHE) injection.
27. The EEPROM device of claim 26 , wherein said charge trapping layer comprises nitride or oxynitride.
28. The EEPROM device of claim 26 , wherein each of said first and second insulating layers comprises oxide.
29. The EEPROM device of claim 26 , wherein said first or said second insulating layer comprises a high-k material.