Array substrate for liquid crystal display device comprising four contact holes in each of the gate pad, data pad, capacitor electrode, and drain electrode
An array substrate for an LCD device and a manufacturing method thereof. The array substrate includes: a gate line, a gate electrode, a gate pad, and a pixel electrode formed on the substrate; a gate insulation layer formed on the substrate to expose the gate line and the pixel electrode; a source electrode connected to a data line crossing the gate line, a drain electrode facing the source electrode with a channel interposed, a data pad formed at one end of the data line, and a capacitor electrode overlapping portions of the pixel electrode and the gate line; a semiconductor layer constituting the channel between the source electrode and the drain electrode; first, second, third, and fourth contact holes formed in the gate pad, the data pad, the capacitor electrode, and the drain electrode, respectively; and first through fourth contact electrodes formed in the first through fourth contact holes, respectively.
1. An array substrate for an LCD (liquid crystal display) device, the array substrate comprising:
a gate line, a gate electrode, a gate pad, and a pixel electrode formed on the substrate;
a gate insulation layer formed on the substrate excluding a portion of the pixel electrode;
a source electrode connected to a data line crossing the gate line, a drain electrode facing the source electrode, a data pad formed at one end of the data line, and a capacitor electrode overlapping portions of the pixel electrode and the gate line;
a semiconductor pattern including a channel between the source and drain electrodes;
first, second, third, and fourth contact holes formed in each of the gate pad, the data pad, the capacitor electrode, and the drain electrode; and
first, second, third, and fourth contact electrodes formed in the first, second, third, and fourth contact holes, respectively.
2. The array substrate according to claim 1 , wherein the first, second, third, and fourth contact electrodes side-contact the gate pad, the data pad, the capacitor electrode, and the drain electrode, respectively.
3. The array substrate according to claim 1 , wherein the gate line, the gate electrode, and the gate pad each include a stack of a transparent electrode pattern and a non-transparent electrode layer.
4. The array substrate according to claim 1 , wherein the data line, the source electrode, the drain electrode, the capacitor electrode, and the data pad each include a stack of the semiconductor pattern and a non transparent electrode layer.
5. The array substrate according to claim 1 , further comprising stacked patterns of the semiconductor layer and a non-transparent electrode layer formed on the gate pad.
6. The array substrate according to claim 1 , further comprising a channel passivation layer made of one of a silicon oxide layer and a silicon nitride layer formed on the channel.
7. The array substrate according to claim 1 , wherein a metal oxide layer is formed on the source and drain electrodes, the gate and data pads, and the gate line.
8. The array substrate according to claim 1 , wherein the drain electrode contacts the pixel electrode via the first contact electrode formed inside the first contact hole.
9. The array substrate according to claim 1 , wherein the capacitor electrode contacts the pixel electrode via the second contact electrode formed inside the second contact hole.
10. The array substrate according to claim 1 , wherein the third contact electrode formed inside the third contact hole contacts the gate pad.
11. The array substrate according to claim 1 , wherein the fourth contact electrode formed inside the fourth contact hole contacts the data pad.