Apparatus for manufacturing a multilayer chip capacitor
The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.
1. An apparatus for manufacturing a multi-layer chip capacitor under a high vacuum, comprising:
a chamber;
a revolving body mounted to revolve in an upper side of the chamber;
a plurality of mask assemblies rotatably installed on a circumference of the revolving body;
a mask set in each mask assembly, each mask set including a shadow mask, the mask sets movable in any horizontal or vertical direction relative to the mask assembly;
a substrate positioned on an upper side of the shadow mask and parallel to the shadow mask; and
a dielectric layer deposition source and a conductor layer deposition source installed on a bottom of the chamber,
wherein the dielectric layer deposition source is positioned perpendicular to the shadow mask and the conductor layer deposition source is positioned oblique to the shadow mask.
2. The apparatus for manufacturing a multi-layer chip capacitor according to claim 1 , wherein the dielectric layer deposition source comprises a dielectric multi-deposition source in which a core rod made by sintering a first dielectric deposition material is inserted into and integrated with an outer pipe made by sintering a second dielectric deposition material.
3. The apparatus for manufacturing a multi-layer chip capacitor according to claim 2 , wherein a diameter of the core rod and the outer pipe are determined based on mol % of the components of the deposition film.
4. The apparatus for manufacturing a multi-layer chip capacitor according to claim 1 , further comprising a conductor index drum for accommodating the conductor layer deposition source and an insulation cap installed in the conductor index drum to thermally insulate the conductor layer deposition source from the exterior.
5. The apparatus for manufacturing a multi-layer chip capacitor according to claim 1 , wherein each mask set has an upper frame and a lower frame, and
wherein each shadow mask has a hold supporting part, the hold supporting part being coupled between the upper frame and lower frame by a wedge shaped coupling.
6. The apparatus for manufacturing a multi-layer chip capacitor according to claim 5 , further comprising a conductor index drum for accommodating the conductor layer deposition source and an insulation cap installed in the conductor index drum to thermally insulate the conductor layer deposition source from the exterior.
7. The apparatus for manufacturing a multi-layer chip capacitor according to claim 5 , wherein the upper and lower mask sets have an upper frame and a lower frame, respectively, and
Wherein each shadow mask has a hold supporting part, the hold supporting part being coupled between the upper frame and the lower frame by a wedge shaped coupling.
8. The apparatus for manufacturing a multi-layer chip capacitor according to claim 1 , further comprising a plasma beam projector for projecting a plasma beam into the vacuum deposition room to give a shock to particles evaporated from the conductor layer deposition source and the dielectric layer deposition source.
9. An apparatus for manufacturing a multi-layer chip capacitor comprising:
a chamber;
a revolving body mounted to revolve in an upper side of the chamber;
a plurality of mask assemblies rotatably installed on a circumference of the revolving body;
each mask assembly having a shadow mask and an upper and lower mask set facing each other and moved by a horizontal mover and a vertical mover;
a substrate installed above and parallel to the shadow mask, the shadow mask moved to form slit patterns; and
a dielectric layer deposition source, a conductor layer deposition source, and respective deposition source evaporators thereof, installed on the bottom of the chamber such that particles evaporated from the deposition sources pass through the slit patterns to be deposited on the substrate.