Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same that reduces a process defect caused by pattern dependency in chemical mechanical polarization (CMP) or etching is excellent. The semiconductor device includes a device pattern formed on or in a substrate; and a plurality of dummy patterns having different longitudinal-sectional areas formed at one side of the device pattern. The dummy patterns, which have the same planar size but have different longitudinal-sectional areas from the three-dimensional structural point of view, include first dummy pattern having a first thickness and second dummy pattern having a second thickness larger than the first thickness.
1. A semiconductor device comprising:
a device pattern formed adjacent to a substrate; and
a plurality of dummy patterns having different longitudinal-sectional areas formed at one side of the device pattern,
wherein the device pattern comprises a shallow trench isolation pattern formed in the substrate and the plurality of dummy patterns comprises a first dummy pattern formed at one side of the device pattern at a first thickness and a second dummy pattern formed at a second thickness larger than the first thickness,
wherein the first dummy pattern and the second dummy pattern are mutually formed in a lattice shape,
wherein a surface profiles of a gap fill on the plurality of dummy patterns is adjusted according to the different depth of the plurality of dummy patterns.
2. The semiconductor device of claim 1 , wherein the device pattern comprises a poly pattern formed on the substrate and the plurality of dummy patterns comprises a first dummy pattern formed at one side of the device pattern to a first height relative to the uppermost surface of the substrate and a second dummy pattern formed to a second height less than the first height.
3. The semiconductor device of claim 1 , wherein the device pattern comprises a metal pattern formed on the substrate and the plurality of dummy patterns comprises a first dummy pattern formed at one side of the device pattern to a first height relative to the uppermost surface of the substrate and a second dummy pattern formed to a second height less than the first height.
4. The semiconductor device of claim 1 , wherein the plurality of dummy patterns have the same planar size.
5. The semiconductor device of claim 1 , wherein the plurality of dummy patterns have different planar sizes.