Wordline driving circuit of semiconductor memory device

1. A semiconductor memory device, comprising:

a main wordline driving unit configured to activate a main wordline according to decoded address information;

a sub wordline driving unit configured to supply a wordline driving voltage to a sub wordline corresponding to the main wordline, the sub wordline being connected to a plurality of cells; and

a bias generator configured to generate a threshold voltage of a MOS transistor in response to an active command

wherein after the main wordline is activated, a voltage level of the main wordline is increased to a level of the threshold voltage of the MOS transistor using a power-supply voltage so as to prevent the sub wordline from being floated,

wherein the main wordline driving unit supplies the power-supply voltage for a predetermined time after the main wordline is activated and transfers threshold voltage from the bias generator after the predetermined time.

2. The semiconductor memory device as recited in claim 1 , wherein the sub wordline driving unit supplies the wordline driving voltage to the sub wordline for accessing the cells when the main wordline is activated and the wordline driving voltage is activated; and

the sub wordline driving unit supplies a ground voltage to the sub wordline using a voltage level of the main wordline when the wordline driving voltage is not activated although the main wordline is activated.

3. The semiconductor memory device as recited in claim 1 , wherein the main wordline driving unit comprises:

an over-driver configured to supply the power-supply voltage and transfer the threshold voltage; and

a plurality of wordline drivers configured to activate the main wordline using a signal output from the over-driver according to the decoded address information.

4. The semiconductor memory device as recited in claim 3 , wherein the over-driver comprises:

a first driver configured to transfer the power-supply voltage instead of the threshold voltage for the predetermined time;

a transmitter configured to output a voltage, obtained by subtracting the threshold voltage from a core voltage, to the wordline drivers in response to a signal output from the first driver;

a transfer controller configured to transfer the core voltage to the transmitter;

a second driver configured to output a ground voltage to deactivate the main wordline when the active command is deactivated or a pre-charge command is activated; and

a controller configured to determine operating times of the first driver, the transmitter, the transfer controller, and the second driver.

5. The semiconductor memory device as recited in claim 4 , wherein the controller controls the first driver in response to a cell matrix select signal activated by the active command, and a first control pulse generated for activating the first driver for the predetermined time;

the controller controls the transmitter and the transfer controller in response to the cell matrix select signal, a sense amp enable signal, a threshold voltage change pulse activated after the predetermined time, and a voltage keeping end pulse activated after a data accessing operation; and

the controller controls the second driver in response to the cell matrix select signal, the sense amp enable signal, and the voltage keeping end pulse.

6. The semiconductor memory device as recited in claim 4 , wherein the controller and the first driver operate using the power-supply voltage, the transfer controller operates using the core voltage having a level lower than the power-supply voltage.

7. The semiconductor memory device as recited in claim 3 , wherein the wordline drivers deactivate the main wordline to a high logic level according to the decoded address information.

8. A semiconductor memory device, comprising:

a main wordlines;

a sub wordlines connected to the main wordlines;

a wordline control circuit configured to maintain an activated main wordline at a level of a threshold voltage of a MOS transistor so as to prevent the sub wordlines from being floated; and

a plurality of bias generators, each provided for each one or two banks and configured to generate the threshold voltage of the MOS transistor in response to an active command,

wherein the wordline control circuit supplies a power-supply voltage for a predetermined time after the main wordline is activated and transfers the threshold voltage from the bias generator after the predetermined time.

9. The semiconductor memory device as recited in claim 8 , wherein the wordline control circuit comprises:

a main wordline driving unit configured to increase a level of the main wordline to a level of the threshold voltage of the MOS transistor using a power-supply voltage for a predetermined time after activating the main wordline according to decoded address information; and

a sub wordline driving unit configured to supply a wordline driving voltage to the sub wordline corresponding to the main wordline, the sub wordline being connected to a plurality of cells.

10. The semiconductor memory device as recited in claim 9 , wherein the main wordline driving unit comprises:

an over-driver configured to supply the power-supply voltage for the predetermined time and transfer a signal output from the bias generator after the predetermined time; and

a plurality of wordline drivers configured to activate the main wordline using a signal output from the over-driver according to the decoded address information.

11. The semiconductor memory device as recited in claim 10 , wherein the over-driver comprises:

a first driver configured to transfer the power-supply voltage instead of the threshold voltage for the predetermined time;

a transmitter configured to output a voltage, obtained by subtracting the threshold voltage from a core voltage, to the wordline drivers in response to a signal output from the first driver;

a transfer controller configured to transfer the core voltage to the transmitter;

a second driver configured to output a ground voltage to deactivate the main wordline when the active command is deactivated or a pre-charge command is activated; and

a controller configured to determine operating times of the first driver, the transmitter, the transfer controller, and the second driver.

12. The semiconductor memory device as recited in claim 9 , wherein the sub wordline driving unit supplies the wordline driving voltage to the sub wordline for accessing the cells when the main wordline is activated and the wordline driving voltage is activated; and

the sub wordline driving unit supplies a ground voltage to the sub wordline using a voltage level of the main wordline when the wordline driving voltage is not activated although the main wordline is activated.

13. A method for operating a semiconductor memory device, the method comprising:

generating a threshold voltage of a MOS transistor in response to an active command;

activating a main wordline according to decoded address information; and

supplying a wordline driving voltage to a sub wordline corresponding to the main wordline and connected to a plurality of cells,

wherein a voltage level of the main wordline is increased to a level of the threshold voltage of the MOS transistor using a power-supply voltage for a predetermined time after the main wordline is activated, so as to prevent the sub wordline from being floated,

wherein the wordline driving voltage is the power-supply voltage for a predetermined time after the main wordline is activated and is the threshold voltage after the predetermined time.

14. The method as recited in claim 13 , wherein the activating of the main wordline comprises:

pulling up the voltage level of the main wordline by transferring the power-supply voltage to the main wordline instead of transferring the threshold voltage to the main wordline for the predetermined time according to the decoded address information; and

transferring the threshold voltage to the main wordline after the predetermined time.