Dynamically setting burst length of double data rate memory device by applying signal to at least one external pin during a read or write transaction
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
1. A method comprising:
receiving a read or write command request on a double data rate memory device having separate groups of external pins adapted to receive address, data, and control information; and
setting a burst length of the double data rate memory device according to a signal input to an address pin of the double data rate memory device proximate in time to receipt of the read or write command.
2. The method of claim 1 , wherein the burst length is set with receipt of a read command.
3. The method of claim 1 , wherein the burst length is set with receipt of a write command.
4. The method of claim 1 , wherein the address pin at which the burst length is set is connected to control logic of the double data rate memory device and column access circuitry, such that burst length is set with a column addressing portion of the read or write command.
5. The method of claim 1 , wherein the address pin is A 12 .
6. The method of claim 1 , further including a step of determining whether a fixed burst length is set.
7. The method of claim 1 , wherein depending on a logic value of the signal input to the address pin, burst length is varied between 4 and 8 bytes.
8. A method comprising:
setting a burst length of a double data rate memory device by applying a signal to a single one of a plurality of external pins of the double data rate memory device, the plurality of external pins being grouped for address, control and data input; and
substantially simultaneously processing a read or write command on the double data rate memory device according to the burst length set at the single external pin such that data is read from or written to the double data rate memory device in burst length sized segments.
9. The method of claim 8 , wherein depending on a logic value of the signal input to the single external pin, burst length is varied between 4 and 8 bytes.
10. The method of claim 8 , wherein if the logic value applied to the single external pin is high, the burst length is set to 8 bytes, and if the logic value applied to the external pin is low, the burst length is set to 4 bytes.
11. The method of claim 8 , wherein the external pin at which burst length is set is an address pin.
12. The method of claim 11 , wherein the address pin is A 12 .
13. A double data rate memory device comprising:
separate external pins for address, control and data input; and
a control logic circuit for controlling operations of the double data rate memory device, the control logic circuit being responsive to a signal received at one of the address pins to set a burst length on the double data rate memory device, wherein depending on the signals input to the address pin, the burst length is set to 4 or 8 bytes.
14. The double data rate memory device of claim 13 , wherein the burst type is set proximate in time to a column addressing operation.
15. The double data rate memory device of claim 13 , wherein the address pin is A 12 .
16. A system, comprising:
a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information; and
a memory controller adapted to set a burst length of the double data rate memory to 4 or 8 bytes by sending a signal through one of the external pins, such that when a read or write command is sent by the controller, depending on the burst length set, data is sent to or received from the double data rate memory device in burst length sized segments.
17. The system of claim 16 , wherein the burst length is set proximate to when the read or write command is received at the double data rate memory device.
18. The system of claim 16 , wherein the external pin to which the burst length setting signal is sent by the memory controller is an address pin.
19. The system of claim 18 , wherein the address pin is A 12 .
20. The system of claim 16 , further comprising a peripheral device adapted to access the double data rate memory device through the memory controller.