IP Library › Granted Patent US 7,986,726
Granted Patent B2
US 7,986,726 · App. 11/267,829 · Granted Jul 26, 2011

CMOS transceiver for communication system

Assignee: Realtek Semiconductor Corp.
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Quick Facts
Patent No.
US 7,986,726
App. No.
11/267,829
Granted
Jul 26, 2011
Kind
B2
Abstract

A direct conversion ultrawideband transceiver employing three phase locked loops (PLLs). The PLLs are preferably fixed-frequency PLLs that operate continuously, at different frequencies, with a selected frequency determined by selecting the output of one of the three PLLs. The use of three PLLs is suitable for use in a communication system employing frequency hopping across three bands or sub-bands.

Claims (28)

1. A transceiver for use in an communication system, comprising:

a plurality of phase-locked loops (PLLs), each of the PLLs providing a signal at a different frequency;

a plurality of mixers, each of the mixers configured to mix the signal generated from a corresponding PLL of the plurality of PLLs with a radio frequency signal to thereby downconvert the radio frequency signal to baseband;

a low noise amplifier having a cascode common gate stage, receiving the radio frequency signal and providing a plurality of amplified radio frequency signals to the plurality of mixers, wherein

each of the plurality of amplified radio frequency signals being provided to a corresponding one of the plurality of mixers, the low noise amplifier including a corresponding plurality of amplifiers each coupled to a resonant tank and selectively activated by a selection signal; and

gate circuitry responsive to the selection signal, the gate circuitry gating the signals provided by the PLLs such that only the signal from a single PLL is provided to one mixer at a given time.

2. The transceiver of claim 1 wherein the PLLs are fixed frequency PLLs.

3. The transceiver of claim 1 wherein the PLLs are fixed modulus PLLs.

4. The transceiver of claim 1 further comprising a summer configured to receive and sum signals from the plurality of mixers.

5. The transceiver of claim 1 further comprising a further mixer, the further mixer receiving a baseband signal for transmission and a mixing signal generated from one of the PLLs.

6. The transceiver of claim 5 further comprising additional gate circuitry and a further summer, the additional gate circuitry gating signals generated from the PLLs in response to the selection signal such that only a signal from a single PLL passes the additional gate circuitry, with the further summer configured to receive signals from the gate circuitry, sum the signals, and provide the summed signal to the further mixer as the mixing signal.

7. The transceiver of claim 4 further comprising a filter filtering the summed signal from the summer.

8. A transceiver for use in an communication system communicating data over three frequency sub-bands in a frequency hopping manner, comprising:

three phase-locked loops (PLLs) each providing a mixing signal at a different frequency;

a low noise amplifier having a cascode common gate stage, receiving a radio frequency (RF) signal and providing three amplified RF signals to three direct downconvert mixers, wherein

each of the three amplified RF signals being provided to a corresponding one of the three direct downconvert mixers, the low noise amplifier including a corresponding plurality of amplifiers each coupled to a resonant tank and selectively activated by a sub-band select signal;

the three direct downconvert mixers each receiving an amplified RF signal and a the mixing signal from a corresponding one of the three PLLs; and

means for gating the mixing signals from the PLLs responsive to the sub-band select signal such that only one of the three direct downconvert mixers receives the mixing signal from the PLLs at a selected time.

9. The transceiver of claim 8 further comprising a further mixer, the further mixer upconverting a baseband signal to an RF signal based on a mixing signal from the PLLs; and means for gating the mixing signals from the PLLs responsive to the sub-band signal such that the further mixer receives only a single mixing signal from the PLLs at a selected time.

10. A transceiver for use in an communication system, comprising:

a low noise amplifier having a cascode common gate stage, receiving a radio frequency (RF) signal and providing a plurality of amplified RF signals each in a separate sub-band to a plurality of mixers, wherein

each of the plurality of amplified RF signals being provided to a corresponding one of the plurality of mixers, the low noise amplifier including a corresponding plurality of amplifiers each coupled to a resonant tank and selectively activated by the sub-band selection signal;

the plurality of mixers, with a mixer for each sub-band used in the communication system, each of the plurality of mixers receiving a representation of the amplified RF signal and configured to receive a mixing signal for direct downconversion of signals in one of the sub-bands used in the communication system;

a plurality of phase-locked loops (PLLs), with a PLL for each sub-band used in the communication system, each of the PLLs generating a mixing signal for direct downconversion of signals in one of the sub-bands used in the communication system; and

means for gating the mixing signals responsive to a sub-band selection signal such that only a single mixer downconverts a representation of the amplified RF signal.

11. The transceiver of claim 10 further comprising a summer summing output signals from the mixers.

12. The transceiver of claim 11 further comprising a filter filtering the summed output signal.

13. The transceiver of claim 10 further comprising a further mixer upconverting a baseband signal to a transmitted radio frequency signal, the further mixer receiving a mixing signal from the PLLs, with the further mixer receiving a single mixing signal at a selected time.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2010
From: WIONICS TECHNOLOGIES, INC. FORMERLY KNOWN AS WIONICS RESEARCH
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 024072/0640 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2006
From: RAZAVI, BEHZAD; KANG, HAN-CHANG; AYTUR, TURGUT; YAN, RAN
To: WIONICS RESEARCH
Reel/Frame 017056/0600 →
Continuity (2)
Provisional Application 60624891 · Nov 3, 2004
Related Publication 20060103473A1 · May 18, 2006