Method and apparatus for adjusting serial data signal

1. A method for adjusting a serial data signal, which comprises a plurality of sets of bits, the method comprising the steps of:

over-sampling one set of bits in said serial data signal to generate a first set of over-sampled bits;

executing a comparison on every adjacent two bits of the first set of over-sampled bits to generate one set of edge bits;

determining a delay operation according to the set of edge bits; and

executing a displacement operation on next sets of bits in the serial data signal according to the delay operation;

wherein the set of edge bits comprises a plurality of sub-sets of the edge bits; and

the step of determining the delay operation comprises:

separately counting the numbers of “1”s corresponding to the sub-sets of the edge bits;

comparing the numbers of “1”s to obtain a reference bit, which is the bit having the maximum number of “1”s in the sub-sets of the edge bits;

controlling a delay phase according to the reference bit to determine the delay operation;

keeping the delay phase when the reference bit is an intermediate bit;

increasing the delay phase when a power of the reference bit is higher than a power of the intermediate bit; and

decreasing the delay phase when the power of the reference bit is lower than the power of the intermediate bit.

2. The method according to claim 1 , wherein an XOR operation is executed on every adjacent two bits of the first set of over-sampled bits to generate the set of edge bits.

3. The method according to claim 1 , further comprising the steps of:

respectively delaying an original clock signal by a plurality of phases to obtain one set of delayed clock signals, which comprises a plurality of sub-sets of the delayed clock signals; and

executing odd-numbered times of over-sampling operations on the set of the bits according to the set of the delayed clock signals so as to generate the first set of the over-sampled bits, wherein each of the delayed clock signals corresponds to one of the over-sampled bits.

4. The method according to claim 3 , further comprising the steps of:

acquiring a next set of over-sampled bits after displacement as one set of parallel bits according to a next one delayed clock signal of an intermediate delayed clock signal of the sub-sets of the delayed clock signals; and

outputting the set of the parallel bits.

5. An apparatus for adjusting a serial data signal, the apparatus comprising:

an over-sampler for receiving the serial data signal to generate one set of over-sampled bits;

an edge extractor for executing a comparison on every adjacent two of the over-sampled bits to generate one set of edge bits;

an edge counter for separately counting the edge bits;

a delay controller coupled to the edge counter and for determining a delay phase for next sets of bits in the serial data signal; and

a digital control delayer for executing a displacement operation on the next sets of the bits according to the delay phase;

wherein the edge counter separately counts the numbers of “1”s corresponding to a plurality of sub-sets of the edge bits, and compares the numbers of “1”s to obtain a reference bit and outputs a parameter according to the reference bit, and the delay controller determines the delay phase according to the parameter; and

when a power of the reference bit is higher than a power of an intermediate bit, the delay controller increases the delay phase according to the parameter.

6. The apparatus according to claim 5 , wherein the serial data signal comprises a plurality of sets of bits, and the over-sampler executes odd-numbered times of over-sampling operations on one of the sets of the bits to generate the set of over-sampled bits.

7. The apparatus according to claim 5 , wherein the edge extractor executes an XOR operation on every adjacent two of the over-sampled bits to generate the set of edge bits, which comprises a plurality of the sub-sets of the edge bits.

8. The apparatus according to claim 5 , wherein the reference bit is the bit having the maximum number of “1”s in the sub-sets of the edge bits.

9. The apparatus according to claim 8 , wherein when the reference bit is the intermediate bit, the delay controller keeps the delay phase according to the parameter.

10. The apparatus according to claim 8 , wherein when a power of the reference bit is lower than a power of the intermediate bit, the delay controller decreases the delay phase according to the parameter.

11. The apparatus according to claim 5 , further comprising:

a phase delay locked loop for respectively delaying an original clock signal by a plurality of phases to obtain one set of delayed clock signals, which comprises a plurality of sub-sets of the delayed clock signals.

12. The apparatus according to claim 11 , wherein the over-sampler executes an over-sampling operation on the serial data signal according to the set of the delayed clock signals so as to generate the set of the over-sampled bits, and each of the delayed clock signals corresponds to one of the over-sampled bits.

13. The apparatus according to claim 12 , further comprising:

a data latch for acquiring a next set of over-sampled bits after displacement as one set of parallel bits according to a next one delayed clock signal of an intermediate delayed clock signal of the sub-sets of the delayed clock signals, and outputting the set of the parallel bits.

14. The apparatus according to claim 11 , further comprising:

a first amplifier for amplifying the original clock signal.

15. The apparatus according to claim 5 , further comprising:

a second amplifier for amplifying the serial data signal.