Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device may include a chip including a chip including a silicon substrate having a semiconductor device area, a pad area and a scribe lane defining an outer contour of the chip. A semiconductor device may be formed in the semiconductor device area, and a pad electrically connected with the semiconductor device may be formed in the pad area. A crack prevention pattern may be formed on an outer contour of the chip, such that the crack prevention pattern extends from a lowest portion to a highest portion of the semiconductor device. A crack prevention pattern is manufactured such that chip cracking can be prevented during the sawing process.
1. An apparatus comprising:
a chip including a silicon substrate having a semiconductor device area, a pad area and a scribe lane, the scribe lane defining an outer contour of the chip;
a semiconductor device formed in the semiconductor device area;
a pad electrically connected with the semiconductor device and formed in the pad area; and
a plurality of crack prevention patterns formed in the scribe lane, wherein each one of the crack prevention patterns extends from a lowest portion to a highest portion of the semiconductor device and is formed apart from other crack prevention patterns.
2. The apparatus of claim 1 , wherein each one of the crack prevention patterns includes:
a first pattern formed over the silicon substrate;
a first insulating layer which covers the first pattern and has a first via pattern connected to the first pattern;
a second pattern connected to the first via pattern on the first insulating layer;
a second insulating layer which covers the second pattern and has a second via pattern connected with the second pattern; and
a third pattern connected with the second via pattern over the second insulating layer.
3. The apparatus of claim 2 , wherein the first, second and third patterns have a width in a range of approximately 10 μm to 20 μm.
4. The apparatus of claim 2 , wherein the first and second via patterns have a width in a range of approximately 0.19 μm to 0.36 μm.
5. The apparatus of claim 2 , wherein the first via pattern has a total number of vias which is equal to a total number of vias in the second via pattern.
6. The apparatus of claim 2 , wherein the first to third patterns are substantially the same size.
7. The apparatus of claim 2 , wherein the first to third patterns overlap.
8. The apparatus of claim 2 , wherein the first and second via patterns are aligned with each other.
9. The apparatus of claim 2 , wherein the first via patterns are formed symmetrically with respect to the second via patterns.