Method of forming a multi-level interconnect structure by overlay alignment procedures

1. A method of manufacturing a semiconductor device, comprising:

forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a first dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area; and

aligning a third layer provided above the structure by using the second alignment mark,

wherein the first dummy pattern provided above the first alignment-mark arrangement area is provided in the second layer and is formed in the same step as the second alignment mark, and

wherein a second dummy pattern is provided in a first part of the third layer, and substantially no dummy pattern is provided in a second part of the third layer, the first part being located above the first alignment-mark arrangement area and the second part being located above the second alignment-mark arrangement area.

2. The method according to claim 1 , wherein the first alignment mark is not used to align any layer that is located higher than the second layer.

3. The method according to claim 1 , wherein a third dummy pattern is formed in a third alignment-mark arrangement area of the third layer, when the third layer is not used to align any layer that is located higher than the third layer.

4. The method according to claim 3 , wherein a fourth dummy pattern is provided below the third alignment-mark arrangement area.

5. The method according to claim 1 , wherein a spare alignment mark is formed in a third alignment-mark arrangement area of the third layer, when the third layer is not used to align any layer that is located higher than the third layer.

6. The method according to claim 1 , wherein providing the first dummy pattern above the first alignment-mark arrangement area is determined on the basis of whether or not the first alignment mark is used for alignment of a layer located higher than the first layer.

7. The method according to claim 1 , wherein the first alignment mark, the second alignment mark, and the first dummy pattern provided above the first alignment-mark arrangement area are provided in a scribe-line region.

8. The method according to claim 1 , wherein the first dummy pattern provided above the first alignment-mark arrangement area is formed in an insulating film.