Semiconductor device with isolation trench liner, and related fabrication methods
A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
1. A method of manufacturing a semiconductor device structure, the method comprising:
providing a substrate having semiconductor material;
forming an isolation trench in the semiconductor material;
lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon, resulting in a lined trench;
at least partially filling the lined trench with an insulating material; and
forming a layer of high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the semiconductor material, such that the liner material divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the semiconductor material.
2. The method of claim 1 , wherein:
at least partially filling the lined trench results in a filled isolation trench and an exposed rim of the liner material; and
forming the layer of high-k gate material comprises depositing the high-k gate material over the filled isolation trench such that the exposed rim of the liner material remains substantially void of the high-k gate material.
3. The method of claim 2 , further comprising forming a metal gate layer over the high-k gate material and over the liner material.
4. The method of claim 3 , further comprising forming a polysilicon gate layer over the metal gate layer.
5. The method of claim 1 , wherein lining the isolation trench comprises lining the isolation trench with a nitride material.
6. The method of claim 1 , wherein at least partially filling the lined trench comprises at least partially filling the lined trench with an oxide material.