IP Library › Granted Patent US 8,001,432
Granted Patent B2
US 8,001,432 · App. 12/274,547 · Granted Aug 16, 2011

Uninitialized memory detection using error correction codes and built-in self test

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,001,432
App. No.
12/274,547
Granted
Aug 16, 2011
Kind
B2
Abstract

An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in response to an occurrence of an event, (ii) read a read word from an address in the memory module in response to a read cycle and (iii) generate an interrupt signal by analyzing the read word, the interrupt signal being asserted where the read word indicates that the address is the uninitialized location in the memory module.

Claims (37)

1. An apparatus comprising:

a memory module; and

an initialization module configured to (i) mark a particular location in said memory module as an uninitialized location by writing a predetermined word into said particular location in response to an occurrence of an event, (ii) read a read word from a given address in said memory module in response to receiving a read command and said given address from another module and (iii) generate an interrupt signal by analyzing said read word, said interrupt signal being asserted where said read word indicates that said given address is an uninitialized location in said memory module, wherein (A) said initialization module is configured to (i) receive a write data value, (ii) generate a write error correction code corresponding to said write data value, (iii) generate a write word by appending said write error correction code to said write data value and (iv) write into said memory module (a) said write word while in a normal mode and (b) said predetermined word while in an initialization mode, (B) said predetermined word comprises a predetermined error correction code and (C) said predetermined error correction code cannot be generated by said initialization module from all possible values of said write data value.

2. The apparatus according to claim 1 , further comprising a built-in self test module configured to transfer an address of said particular location to said initialization module in response to said event.

3. The apparatus according to claim 2 , wherein said built-in self test module is further configured to transfer said predetermined word to said initialization module.

4. The apparatus according to claim 1 , wherein said initialization module analyzes said read word by comparing said read word with said predetermined word, said interrupt signal being (i) asserted where said read word matches said predetermined word and (ii) deasserted otherwise.

5. The apparatus according to claim 1 , wherein (i) said predetermined word comprises a predetermined error correction code and (ii) said initialization module is configured to (a) parse a read error correction code from said read word and (b) analyze said read word by comparing said read error correction code with said predetermined error correction code, said interrupt signal being (1) asserted where said read error correction code matches said predetermined error correction code and (2) deasserted otherwise.

6. The apparatus according to claim 1 , wherein (i) said predetermined word comprises a predetermined error correction code and (ii) said initialization module is configured to (a) parse a read data value and a read error correction code from said read word, (b) generate a recovered error correction code from said read data value and (c) analyze said read word by comparing said recovered error correction code and said read error correction code, said interrupt signal being (1) asserted where said recovered error correction code does not match said read error correction code and (2) deasserted otherwise.

7. The apparatus according to claim 6 , wherein said initialization module is configured to (i) enable correction of said read data value using said read error correction code while in a normal mode and (ii) disable said correction of said read data value while in a non-normal mode.

8. The apparatus according to claim 1 , wherein said other module comprises a processor module configured to capture said given address in response to said assertion of said interrupt signal when reading said given address from said memory module.

9. A method of detecting uninitialized memory, comprising the steps of:

(A) marking a particular location in a memory module as an uninitialized location by writing a predetermined word into said particular location in response to an occurrence of an event;

(B) reading a read word from a given address in said memory module in response to receiving a read command and said given address from another module; and

(C) generating an interrupt signal by analyzing said read word, said interrupt signal being asserted where said read word indicates that said given address is an uninitialized location in said memory module;

(D) receiving a write data value;

(E) generating a write error correction code corresponding to said write data value;

(F) generating a write word by appending said write error correction code to said write data value; and

(G) writing into said memory module (a) said write word while in a normal mode and (b) said predetermined word while in an initialization mode, wherein (i) said predetermined word comprises a predetermined error correction code and (ii) said predetermined error correction code cannot be generated by an error correction code technique from all possible values value of said write data value.

10. The method according to claim 9 , wherein said analysis is performed at all of a plurality of addressable locations of said memory module.

11. The method according to claim 9 , further comprising the step of:

capturing said given address in said other module in response to said assertion of said interrupt signal when reading said given address from said memory module.

12. The method according to claim 9 , wherein analyzing said read word comprises the sub-step of:

comparing said read word with said predetermined word, said interrupt signal being (i) asserted where said read word matches said predetermined word and (ii) deasserted otherwise.

13. The method according to claim 9 , wherein:

said predetermined word comprises a predetermined error correction code;

the method further comprises the step of parsing a read error correction code from said read word; and

analyzing said read word comprises the sub-step of comparing said read error correction code with said predetermined error correction code, said interrupt signal being (i) asserted where said read error correction code matches said predetermined error correction code and (ii) deasserted otherwise.

14. The method according to claim 9 , wherein:

said predetermined word comprises a predetermined error correction code;

the method further comprises the steps of (i) parsing a read data value and a read error correction code from said read word and (ii) generating a recovered error correction code from said read data value; and

analyzing said read word comprises the sub-step of comparing said recovered error correction code and said read error correction code, said interrupt signal being (i) asserted where said recovered error correction code does not match said read error correction code and (ii) deasserted otherwise.

15. The method according to claim 14 , further comprising the steps of:

enabling correction of said read data value using said read error correction code while in a normal mode; and

disabling said correction of said read data value while in a non-normal mode.

16. An apparatus comprising:

means for storing; and

means for (i) marking a particular location in said means for storing as an uninitialized location by writing a predetermined word into said particular location in response to an occurrence of an event, (ii) reading a read word from a given address in said means for storing in response to receiving a read command and said given address from a module, (iii) generating an interrupt signal by analyzing said read word, said interrupt signal being asserted where said read word indicates that said given address is an uninitialized location in said means for storing, (iv) receiving a write data value, (v) generating a write error correction code corresponding to said write data value, (vi) generating a write word by appending said write error correction code to said write data value, and (vii) writing into a memory module (a) said write word while in a normal mode and (b) said predetermined word while in an initialization mode, wherein (i) said predetermined word comprises a predetermined error correction code and (ii) said predetermined error correction code cannot be generated by an error correction code technique from all possible values value of said write data value.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2008
From: ORBACH, YAIR; RACHLEVSKI, ASSAF
To: LSI CORPORATION
Reel/Frame 021866/0124 →
Continuity (1)
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