Fault tolerant asynchronous circuits
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
1. A fault tolerant static random access memory (SRAM) circuit, comprising:
a read circuit;
a write circuit;
a staticizer circuit, comprising
first and second C-elements each connected to each of the read and write circuits, and
third and fourth C-elements each connected to an output of each of the first and second C-elements and to the read and write circuits, the staticizer circuit configured to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault; and
a plurality of replicas of the staticizer circuit to process outputs of N logic gates generating N output signals.
2. The circuit of claim 1 , wherein each of the third and fourth C-elements comprises weak C-elements.
3. The circuit of claim 2 , further comprising:
an inverter connected at an output of each of the first C-element, the second C-element, a third weak C-element and a fourth weak C-element, each inverter connecting a pair of C-elements to physically space an input and output of the pair of C-elements.
4. The circuit of claim 2 , wherein at least one of the read and write circuits comprises a pair of series-connected transistors for each signal processing transistor of a plurality of signal processing transistors.
5. The circuit of claim 2 , wherein at least one of the read and write circuits comprises a duplicate circuit connected in parallel with the at least one of the read and write circuits.
6. A fault tolerant static random access memory (SRAM) circuit, comprising:
a read circuit;
a write circuit, at least one of the read and write circuits comprising a pair of series-connected transistors for each signal processing transistor of a plurality of signal processing transistors; and
a staticizer circuit, comprising
first and second C-elements each connected to each of the read and write circuits, and
third and fourth C-elements each connected to an output of each of the first and second C-elements and to the read and write circuits, an output of each of the third and fourth C-elements connected to each of the first and second C-elements, the staticizer circuit configured to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault.
7. The circuit of claim 6 , wherein each of the third and fourth C-elements comprises weak C-elements.
8. The circuit of claim 7 , further comprising:
an inverter connected at an output of each of the first C-element, the second C-element, a third weak C-element and a fourth weak C-element, each inverter connecting a pair of C-elements to physically space an input and output of the pair of C-elements.
9. The circuit of claim 7 , wherein at least one of the read and write circuits comprises a duplicate circuit connected in parallel with the at least one of the read and write circuits.
10. A fault tolerant static random access memory (SRAM) circuit, comprising:
a read circuit;
a write circuit, at least one of the read and write circuits comprising a duplicate circuit connected in parallel with the read and write circuits; and
a staticizer circuit, comprising
first and second C-elements each connected to each of the read and write circuits, and
third and fourth C-elements each connected to an output of each of the first and second C-elements and to the read and write circuits, an output of each of the third and fourth C-elements connected to each of the first and second C-elements, the staticizer circuit configured to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault.
11. The circuit of claim 10 , wherein each of the third and fourth C-elements comprises weak C-elements.
12. The circuit of claim 11 , further comprising:
an inverter connected at an output of each of the first C-element, the second C-element, a third weak C-element and a fourth weak C-element, each inverter connecting a pair of C-elements to physically space an input and output of the pair of C-elements.
13. The circuit of claim 11 , wherein at least one of the read and write circuits comprises a pair of series-connected transistors for each signal processing transistor of a plurality of signal processing transistors.
14. A method comprising:
connecting each of first and second C-elements of a staticizer circuit to a read and a write circuit;
connecting each of third and fourth C-elements of the staticizer circuit to an output of each of the first and second C-elements and to the read and write circuits;
configuring the staticizer circuit to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault; and
connecting a plurality of replicas of the staticizer circuit to process outputs of N logic gates generating N output signals.
15. The method of claim 14 , wherein each of the third and fourth C-elements comprises weak C-elements.
16. The method of claim 15 , further comprising:
connecting an inverter at an output of each of the first C-element, the second C-element, a third weak C-element and a fourth weak C-element, each inverter connecting a pair of C-elements to physically space an input and output of the pair of C-elements.
17. The method of claim 15 , further comprising:
configuring at least one of the read and write circuits as a pair of series-connected transistors for each signal processing transistor of a plurality of signal processing transistors.
18. The method of claim 15 , further comprising:
duplicating at least one of the read and write circuits connected in parallel with the at least one of the read and write circuits.
19. A method comprising:
connecting each of first and second C-elements of a staticizer circuit to a read and a write circuit, at least one of the read and write circuits comprising a pair of series-connected transistors for each signal processing transistor of a plurality of signal processing transistors;
connecting each of third and fourth C-elements of the staticizer circuit to an output of each of the first and second C-elements and to the read and write circuits, the connecting including connecting an output of each of the third and fourth C-elements to each of the first and second C-elements; and
configuring the staticizer circuit to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault.
20. The method of claim 19 , wherein each of the third and fourth C-elements comprises weak C-elements.
21. The method of claim 20 , further comprising:
connecting an inverter at an output of each of the first C-element, the second C-element, a third weak C-element and a fourth weak C-element, each inverter connecting a pair of C-elements to physically space an input and output of the pair of C-elements.
22. The method of claim 20 , further comprising:
replicating the staticizer circuit to process outputs of N logic gates to generate N output signals.
23. A method comprising:
connecting each of first and second C-elements of a staticizer circuit to a read and a write circuit, at least one of the read and write circuits comprising a duplicate circuit connected in parallel with the read and write circuits;
connecting each of third and fourth C-elements of the staticizer circuit to an output of each of the first and second C-elements and to the read and write circuit, the connecting including connecting an output of each of the third and fourth C-elements to each of the first and second C-elements; and
configuring the staticizer circuit to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault.
24. The method of claim 23 , wherein each of the third and fourth C-elements comprises weak C-elements.
25. The method of claim 24 , further comprising:
connecting an inverter at an output of each of the first C-element, the second C-element, a third weak C-element and a fourth weak C-element, each inverter connecting a pair of C-elements to physically space an input and output of the pair of C-elements.
26. The method of claim 24 , further comprising:
replicating the staticizer circuit to process outputs of N logic gates to generate N output signals.
27. A method to render a static random access memory (SRAM) circuit fault tolerant, the method comprising:
interconnecting a read circuit, a write circuit, and a staticizer circuit;
connecting each of first and second C-elements of the staticizer circuit to each of the read and write circuits;
connecting each of third and fourth C-elements of the staticizer circuit to an output of each of the first and second C-elements and to the read and write circuits;
configuring the staticizer circuit to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault; and
connecting a plurality of replicas of the staticizer circuit to process outputs of N logic gates generating N output signals.
28. A method to render a static random access memory (SRAM) circuit fault tolerant, the method comprising:
interconnecting a read circuit, a write circuit, and a staticizer circuit, at least one of the read and write circuits comprising a duplicate circuit connected in parallel with the read and write circuits;
connecting each of first and second C-elements of the staticizer circuit to each of the read and write circuits;
connecting each of third and fourth C-elements of the staticizer circuit to an output of each of the first and second C-elements and to the read and write circuits, the connecting including connecting an output of each of the third and fourth C-elements to each of the first and second C-elements; and
configuring the staticizer circuit to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault.
29. A method to render a static random access memory (SRAM) circuit fault tolerant, the method comprising:
interconnecting a read circuit, a write circuit, and a staticizer circuit, at least one of the read and write circuits comprising a pair of series-connected transistors for each signal processing transistor of a plurality of signal processing transistors;
connecting each of first and second C-elements of the staticizer circuit to each of the read and write circuits;
connecting each of third and fourth C-elements of the staticizer circuit to an output of each of the first and second C-elements and to the read and write circuits, the connecting including connecting an output of each of the third and fourth C-elements to each of the first and second C-elements; and
configuring the staticizer circuit to prevent a single write from changing an overall state of the SRAM circuit during a time-limited fault.