IP Library Granted Patent US 8,004,896
Granted Patent B2
US 8,004,896 · App. 12/493,604 · Granted Aug 23, 2011

Method of controlling operation of flash memory device

Assignee: Hynix Semiconductor Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,004,896
App. No.
12/493,604
Granted
Aug 23, 2011
Kind
B2
Abstract

According to a method of controlling the operation of a flash memory device including a number of memory blocks, a memory block of the memory blocks is first selected as a reference block. A program operation is performed on a memory cell included in the reference block. In order to check an operating characteristic of the reference block, a threshold voltage level of the programmed memory cell is read. Parameters for performing an operation of the flash memory device are determined based on the operating characteristic of the reference block. The parameters are stored in the reference block.

Claims (24)

1. A method of controlling an operation of a flash memory device, the method comprising:

selecting a memory block of a number of memory blocks of a flash memory device as a reference block;

performing a program operation on a memory cell included in the reference block;

reading a threshold voltage level of the programmed memory cell in order to check an operating characteristic of the reference block;

determining at least one parameter for an operation of the flash memory device based on the operating characteristic of the reference block; and

storing the at least one parameter in the reference block.

2. The method of claim 1 , wherein the at least one parameter comprises one of a start voltage and a step voltage for performing an Incremental Step Pulse Program (ISPP) operation, a program verification voltage, and a read voltage for performing a read operation.

3. The method of claim 2 , wherein the determination of the ISPP step voltage of one of the at least one parameter comprises:

setting a preliminary read voltage to be lower than a read voltage used in a read operation;

counting a number of memory cells, each having a threshold voltage lower than the preliminary read voltage, by reading the memory cells on the basis of the preliminary read voltage; and

reducing the ISPP step voltage value when the number of memory cells each having the threshold voltage lower than the preliminary read voltage is reduced as compared with an initial program cycle operation due to widening of a threshold voltage distribution with repetition of program cycle operations.

4. The method of claim 3 , wherein the ISPP step voltage value is reduced by 0.05 V.

5. The method of claim 2 , wherein the determination of the ISPP step voltage of the at least one parameter comprises:

setting a preliminary read voltage to be lower than a read voltage used in a read operation;

counting a number of memory cells, each having a threshold voltage lower than the preliminary read voltage, by reading the memory cells on the basis of the preliminary read voltage; and

reducing the ISPP start voltage value when the number of memory cells each having the threshold voltage lower than the preliminary read voltage is reduced as compared with an initial program cycle operation due to widening of a threshold voltage distribution with repetition of program cycle operations.

6. The method of claim 1 , wherein when the flash memory device is in an idle time, the reference block is selected.

7. The method of claim 1 , wherein the reference block is selected using a wear level control method.

8. The method of claim 1 , wherein the parameters are stored in a last page of the reference block.

9. The method of claim 1 , further comprising:

storing parameters in a control unit, wherein the parameters stored in the control unit are determined based on an operating characteristic of a reference block included in the flash memory device and are stored in the same reference block; and

performing a program or read operation on the flash memory device using the parameters stored in the control unit.

10. The method of claim 9 , wherein when a number of program cycles for the flash memory device are 100 times, the parameters are stored in the control unit.

11. The method of claim 9 , wherein when the flash memory device is rebooted, the parameters are stored in the control unit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2009
From: JOO, SEOK JIN
To: HYNIX SEMICONDUCTOR, INC.
Reel/Frame 022887/0257 →
Priority Claims (1)
KR 10-2008-0076373 · Aug 5, 2008 · national
Continuity (1)
Related Publication 20100034021A1 · Feb 11, 2010