Phase change memory cell with heater and method for fabricating the same
A memory device with a thin heater forms a programmable resistive change region in a sub-lithographic pillar of programmable resistive change material (“memory material”), where the heater is formed within the pillar between the top electrode and the programmable material. The device includes a dielectric material layer and vertically separated top and bottom electrodes having mutually opposed contact surfaces. A sub-lithographic pillar of memory material, which in a particular embodiment is a chalcogenide, is encased within the dielectric material layer. A heater between the pillar of programmable resistive material and the top electrode forms an active region, or programmable resistive change region, next to the heater when the memory device is programmed or reset.
1. A memory device comprising:
a bottom electrode;
a dielectric fill layer having a top surface;
a top electrode, on the top surface of the dielectric fill layer;
a sub-lithographic pillar of memory material disposed between the bottom electrode and the top electrode within the dielectric fill layer, the memory material being programmable to a plurality of resistive states by heating;
a heater consisting of a heater material having a resistivity greater than that of the top electrode and greater than that of the memory material in its most highly resistive state disposed on the sub-lithographic pillar of memory material within the dielectric fill layer between the top electrode and the sub-lithographic pillar of memory material, the heater having a top surface in direct contact with the top electrode; and
a programmable resistive change region in the sub-lithographic pillar of memory material selectively programmable by resistively heating the heater so as to convert the programmable resistive change region from a first resistive state to a second resistive state, the programmable resistive change region being confined to a part of the sub-lithographic pillar adjacent to the heater, wherein the sub-lithographic pillar of memory material has a diameter, and the heater has a diameter, wherein the diameter of the heater is the same as the diameter of the sub-lithographic pillar of memory material.
2. The memory device of claim 1 , wherein the memory material comprises a combination of Ge, Sb, and Te.
3. The memory device of claim 1 , wherein the sub-lithographic pillar of memory material has a height of between about 20 and 120 nm.
4. The memory device of claim 1 , wherein the sub-lithographic pillar of memory material has a height of about 80 nm.
5. The memory device of claim 1 , wherein the memory material comprises a chalcogenide.
6. The memory device of claim 1 , wherein the memory material comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.
7. The memory device of claim 1 , wherein the top electrode comprises a bit line.
8. The memory device of claim 7 wherein the bit line is disposed on the heater.
9. The memory device of claim 1 , wherein the heater material comprises at least one of silicon carbide, graphite, tantalum nitride, tantalum-aluminum nitride, tungsten nitride, aluminum oxide and tantalum oxide.
10. A memory device comprising:
a bottom electrode;
a dielectric fill layer;
a top electrode, over the dielectric fill layer;
a sub-lithographic pillar of memory material disposed between the bottom electrode and the top electrode within the dielectric fill layer, the memory material being programmable to a plurality of resistive states by heating;
a heater consisting of a heater material having a resistivity greater than that of the top electrode and greater than that of the memory material in its most highly resistive state disposed on the sub-lithographic pillar of memory material within the dielectric fill layer between the top electrode and the sub-lithographic pillar of memory material, the heater having a top surface in direct contact with the top electrode, wherein the sub-lithographic pillar of memory material has a diameter, and the heater has a diameter, wherein the diameter of the heater is the same as the diameter of the sub-lithographic pillar of memory material; and
a programmable resistive change region in the sub-lithographic pillar of memory material selectively programmable by resistively heating the heater so as to convert the programmable resistive change region from a first resistive state to a second resistive state, the programmable resistive change region being confined to a part of the sub-lithographic pillar adjacent to the heater, wherein the heater material comprises dielectric material not more than 2 nm thick.
11. The memory device of claim 1 wherein the heater material comprises at least one of silicon carbide and graphite.
12. The memory device of claim 1 , wherein the top surface of the heater is co-planar with the top surface of the dielectric fill layer.
13. The memory device of claim 10 , wherein the top surface of the heater is co-planar with the top surface of the dielectric fill layer.