Electrical connector system
High-speed backplane connectors systems for mounting a substrate that are capable of operating at speeds of up to at least 25 Gbps, while in some implementations also providing pin densities of at least 50 pairs of electrical connectors per inch are disclosed. Implementations of the high-speed connector systems may provide ground shields and/or other ground structures that substantially encapsulate electrical connector pairs, which may be differential electrical connector pairs, in a three-dimensional manner throughout a backplane footprint, a backplane connector, and a daughtercard footprint. These encapsulating ground shields and/or ground structures prevent undesirable propagation of non-traverse, longitudinal, and higher-order modes when the high-speed backplane connector systems operates at frequencies up to at least 30 GHz.
1. A header assembly for mounting an electrical connector to a substrate, the header assembly comprising:
a plurality of ground shields, each ground shield defining at least one ground substrate engagement element at a mounting face of the header assembly; and
a plurality of signal pins, each signal pin defining a signal substrate engagement element at the mounting face of the header assembly;
wherein each signal pin of the plurality of signal pins is associated with another signal pin of the plurality of signal pin to define a signal pin pair;
wherein the ground substrate engagement elements and signal substrate engagement elements are positioned on the mounting face of the header assembly such that there is at least one ground substrate engagement element positioned directly between each signal substrate engagement element and any of the closest non-paired signal substrate engagement element neighbors.
2. The header assembly of claim 1 , wherein at least a portion of the plurality of grounds shields are C-shaped ground shields.
3. The header assembly of claim 1 , wherein the signal substrate engagement elements comprise signal mounting pins.
4. The header assembly of claim 1 , wherein the ground substrate engagement elements comprise ground mounting pins.
5. The header assembly of claim 1 , wherein signal substrate engagement elements of the plurality of signal pins are positioned on the mounting face of the header assembly in a matrix of rows and columns.
6. The header assembly of claim 5 , wherein a first row of signal substrate engagement elements is aligned with a second row of signal substrate engagement elements that is adjacent to the first row of signal substrate engagement elements.
7. The header assembly of claim 5 , wherein a first row of signal substrate engagement elements is offset from a second row of signal substrate engagement elements that is adjacent to the first row of signal substrate engagement elements.
8. A plurality of wafer assemblies configured to mount to a substrate, the plurality of wafer assemblies comprising:
a plurality of electrical contact mounting pins positioned on a mounting end of the plurality of wafer assemblies, the electrical contact mounting pins arranged in a matrix of rows and columns at the mounting end, each electrical contact mounting pin associated with one of its closest neighbor electrical contact mounting pins to form a pair;
a plurality of ground mounting pins positioned on the mounting end of the plurality of wafer assemblies, the plurality of ground mounting pins capable of being commoned to one another;
wherein the ground mounting pins are positioned amongst the plurality of electrical contact mounting pins such that there is at least one ground mounting pin positioned directly between each electrical contact mounting pin and any of the closest non-paired electrical contact mounting pin neighbors.
9. The plurality of wafer assemblies of claim 8 , wherein the plurality of wafer assemblies comprise a first row of electrical contact mounting pins that is aligned with a second row of electrical contact mounting pins that is adjacent to the first row of electrical contact mounting pins.
10. The plurality of wafer assemblies of claim 8 , wherein the plurality of wafer assemblies comprise a first row of electrical contact mounting pins that is offset from a second row of electrical contact mounting pins that is adjacent to the first row of electrical contact mounting pins.
11. The plurality of wafer assemblies of claim 8 , wherein the substrate is a printed circuit board.
12. The plurality of wafer assemblies of claim 8 , wherein the plurality of grounds mounting pins is capable of being electrically connected to a common ground.