IP Library › Granted Patent US 8,018,284
Granted Patent B2
US 8,018,284 · App. 12/649,376 · Granted Sep 13, 2011

Method of using integrated power amplifier

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Quick Facts
Patent No.
US 8,018,284
App. No.
12/649,376
Granted
Sep 13, 2011
Kind
B2
Abstract

An output-impedance in a power amplifier is provided. A first transistor Q BUF of a buffer stage is connected to a first side of a resistor R F and a second transistor Q AMP to a second opposite side of the resistor R F . The first transistor feeds a current I RF to the second resistor Q AMP . The current I RF at the second transistor is copied and multiplied by a factor (n) to form an output current I OUT , as (1+n)*I RF . The current I RF is fed back to the first transistor and the output current I OUT is fed to a load resistor R.

Claims (13)

1. A method for providing an output-impedance in a power amplifier, comprising:

connecting a first transistor (Q BUF ) on a first side of a impedance (R F ) and a second transistor (Q AMP ) to a second opposite side of the impedance (R F ),

the first transistor feeding a current (I RF ) to the impedance (R F ),

copying the current (I RF ) at the second transistor,

multiplying the current with a factor (n) to form an output current (I OUT ), as (1+n)*(I RF ),

feeding back the current (I RF ) to the first transistor,

feeding the output current (I OUT ) to a load resistor (R), and

using an additional impedance (R G ) to load a buffer stage and increasing the output power without affecting any output impedance of the power amplifier.

2. The method according to claim 1 wherein the method further comprises providing a buffer stage having the first transistor Q BUF .

3. The method according to claim 2 wherein the method further comprises buffering an input voltage (V IN ) to a source voltage VS in the buffer stage.

4. The method according to claim 1 wherein the method further comprises feeding back the current (I RF ) via the impedance (R F ) to a buffer stage.

5. The method according to claim 1 wherein the method further comprises using a DC block to prevent direct current voltage from being fed to the load resistor (R).

6. The method according to claim 1 wherein the method further comprises programming the additional impedance (R G ) to gain control of an output power of the output stage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2021
From: CATENA HOLDING B.V.
To: NXP B.V.
Reel/Frame 058153/0538 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2012
From: CARLSSON, MATS; BJORK, DANIEL
To: CATENA HOLDING BV
Reel/Frame 027750/0112 →
Continuity (1)
Related Publication 20110156818A1 · Jun 30, 2011