Memory module for improving signal integrity and computer system having the same
A memory module includes a plurality of buses and a plurality of memory chips arranged close to each other along each of the plurality of buses. An N-th memory chip, where N is an integer, of the plurality of memory chips is connected to any one of the plurality of buses, and each of the other memory chips of the plurality of memory chips, except for the N-th memory chip, is connected to the other one of the plurality of buses.
1. A memory module comprising:
a plurality of buses; and
a plurality of memory chips arranged close to each other along each of the plurality of buses,
wherein an N-th memory chip, where N is an integer, of the plurality of memory chips is connected to one of the plurality of buses, and each of the other memory chips of the plurality of memory chips, except for the N-th memory chip, is connected to another one of the plurality of buses, and
wherein the plurality of memory chips and the plurality of buses, including the one of the plurality of buses and the other one of the plurality of buses, are arranged by a fly-by topology.
2. The memory module of claim 1 , wherein a pattern length between the N-th memory chip and the one of the plurality of buses is longer than a pattern length between each of the other memory chips, except for the N-th memory chip, and the other one of the plurality of buses.
3. The memory module of claim 1 , wherein the N-th memory chip is the first memory chip of the plurality of memory chips.
4. The memory module of claim 1 , wherein the memory module is a registered DIMM (RDIMM) or an unbuffered DIMM (UDIMM).
5. A computer system comprising:
a memory slot;
a memory module electrically connected to the memory slot, in which a plurality of memory chips are arranged; and
a processor controlling input/output operations of the memory module,
wherein the memory module comprises:
a plurality of buses; and
the plurality of memory chips arranged close to each other along each of the plurality of buses,
wherein an N-th memory chip, where N is an integer, of the plurality of memory chips is connected to one of the plurality of buses, and each of the other memory chips of the plurality of memory chips, except for the N-th memory chip, is connected to another one of the plurality of buses, and
wherein the plurality of memory chips and the plurality of buses, including the one of the plurality of buses and the other one of the plurality of buses, are arranged by a fly-by topology.
6. The computer system of claim 5 , wherein a pattern length between the N-th memory chip and the one of the plurality of buses is longer than a pattern length between each of the other memory chips, except for the N-th memory chip, and the other one of the plurality of buses.